Ultrashort Channel Silicon Nanowire Transistors with Nickel Silicide Source/Drain Contacts
Our platform consists of a 50 nm silicon nitride membrane suspended over a window in a TEM-compatible Si carrier. Vapor-Liquid-Solid (VLS) grown Si NWs are transferred to the nitride membranes from solution and photolithography is used to define Ni electrodes to the Si NWs. The reactions are generally formed at 400 C resulting in NiSi2 silicide as the leading phase in contact with silicon. Our experiments show that the silicidation growth shows a signature parabolic diffusion limited behavior. The growth front is preferred over Si (111) planes on both <111> and <112> grown Si NWs. The capability to monitor the silicide growth in real time on an in-situ TEM hot stage allows precise control of Si channel length accuracy of 1nm (Figure a) .
On our 17nm channel device (Figure b), high maximum on-currents of 890 (μA/μm) and a maximum transconductance of 430 (μS/μm) were obtained (Figure c), which pushes forward the performance of bottom-up Si NW Schottky barrier field-effect transistors (SB-FETs). Through accurate control over the silicidation reaction, we provide a systematic study of channel length dependent carrier transport in large number of SB-FETs with channel lengths in the range of (17 nm – 3.6 μm) (Figure d). We developed an convenient analytical expression for gate capacitance in Omega gate configuration with <2% errors to the finite element simulation result. With the careful treatment of gate capacitance, our device results corroborate with our transport simulations and reveal a characteristic type of short channel effects in SB-FETs, both in on- and off-state, that limits transport parameter extraction from SB-FETs using conventional field-effect transconductance measurements. Our data suggest that the Schottky barrier contact engineering is vital to best fulfill performance gains in short channel SB-FETs.
Figure captions: (a) Series of in-situ TEM snapshots showing the growth of nickel silicide from S/D Ni electrodes and narrowing of the middle silicon segment. The red arrows indicate the silicide/silicon reaction front. Scale bar is 1 μm. (b) TEM image of a Si NW FET device with 17 nm channel length. Scale bar is 1 μm. (c) Id-Vg characteristics of Si NW FETs with different channel lengths at Vd=-0.1V at linear (left y-axis) and log (right y-axis) scales. Inset is a schematic of the ultra-short channel Si NW FET device (d) Channel length dependent device performance. Inset is the energy band-edge diagram of Si NW SBFET in on-state.