A Facile Microfabrication Process of Self-Doping SiGe/Si Multi-Quantum Well Arrays for Thermo Electrical Characterization
A 4-inch SOI wafer was used as the handle wafer for the growth of SiGe/Si MQWs. The thickness of silicon handle wafer part silicon on insulator (SOI) wafer is 500 μm with 1.5 μm BOX layer (SiO2). The total 5 periodic thickness of SiGe/Si MQW is 725 nm and grown on the SOI wafer, and then sputtered with 20 nm Ti layer and 70 nm Al layer sequentially. Then a second patterned metallized wafer was electroplated with Au interconnect lines and pads as electrical measurement leads. The two wafers were then bonded together face to face using a wafer-level adhesive wafer bonding . After the bonding, the 500 μm thick Si layer of SOI wafer was removed by inductively coupled plasma (ICP) Etching etching. The ICP stops at the SiO2 layer, and the SiO2 is removed by using regular BOE (buffer oxide etches). The SiGe/Si film was then patterned by lithography and dry etching. With the electroplated Au electrode column connecting the film and the Au pads on target wafer, the thin film was then covered by the 50nm Ti by sputter and the 350nm SiN layer deposited by PECVD for enhancing infrared light absorption. Finally, the whole device layer was patterned by lithography and dry etching, during which the bonding polymer was completely removed by O2 plasma. The released arrays are shown in fig.1. Then, the dependence of current-resistance and the temperature-resistance are examined by the facile metallized leads and the results are shown in fig.2. The TCR (temperature coefficient of resistance) of the arrays is about -2.6%K-1 at 303K. This value is consistent with that of previous reported results .
In summary, a relatively facile microfabrication process has been developed for characterizing the thermoelectrical properties of SiGe/Si MQWs materials. The processed thermalelectrical arrays show an expected TCR value as mathematical simulation.
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