Improved Charge-Trapping Performance of Hf-Doped SrTiO3 for Nonvolatile Memory Applications

Metal-oxide-nitride-oxide-silicon (MONOS) nonvolatile memories with traps in their dielectrics for charge storage have been considered as a better candidate than their conventional floating-gate counterpart due to their localized charge-storage and coupling-free properties. SrTiO₃ was demonstrated to be a promising charge-trapping layer (CTL) for low-voltage MONOS memory applications due to its high-k value as well as large band offset with respect to the SiO₂ tunneling oxide. However, this SrTiO₃-based memory displayed severe charge loss mainly due to its poor thermodynamic stability with SiO₂, which resulted in a thick non-stoichiometric interlayer at the SrTiO₃/SiO₂ interface¹. On the contrary, hafnium oxide has a good thermodynamic stability with SiO₂¹ and is also a well-known material for CTL². Therefore, this work aims to investigate the charge-trapping characteristics of Hf-doped SrTiO₃.

MONOS capacitor with an Al/Al₂O₃/Hf-doped SrTiO₃/SiO₂/Si structure was fabricated. SiO₂ was grown on the p-type Si by thermal oxidation. Then, Hf-doped SrTiO₃ film as CTL was prepared by co-sputtering of Hf and SrTiO₃ targets using a power of 30 W.  Following that, Al₂O₃ as blocking layer was deposited by atomic layer deposition. Finally Al was evaporated and patterned as gate electrode, followed by forming-gas annealing at 300 ^oC for 20 min. No obvious interlayer is observed at the SrTiO₃/SiO₂ interface from the TEM image in Fig. 1(a). This observation can be further confirmed by the XPS analysis shown in Fig. 1(b), where the small area of the silicate component suggests negligible formation of the interlayer resulted from the SrTiO₃/SiO₂ interfacial reaction. Consequently, Hf incorporation in SrTiO₃can effectively improve the thermodynamic stability.

Fig. 2 shows the program/erase (P/E) transient characteristics of the MONOS device with Hf-doped SrTiO₃ as CTL. The proposed device presents higher operating speed (a V_FB shift ΔV_FB ~ 3.5 V at +8 V, 100 μs)  than the one with pure SrTiO₃ as CTL (ΔV_FB ~ 0.7 V)¹, suggesting improved charge-trapping efficiency by Hf incorporation in SrTiO₃. Moreover, the proposed device still shows a ΔV_FB of 1.9 V even at a small gate voltage of +6 V for 100 μs, demonstrating its low-voltage operating ability. Fig. 3 shows the retention characteristic of the proposed device. Compared with the device with SrTiO₃ as CTL which presents severe charge loss¹, the proposed one displays much better data retention ability and the charge loss rate after 10⁴ s is only 12.7%.  The formation of the interlayer at the SrTiO₃/SiO₂ interface consumes part of the SiO₂tunneling oxide (thus shortening the leakage path from the CTL to the substrate), and also the traps in the non-stoichiometric interlayer usually facilitate charge loss. Therefore, the better data retention should be mainly ascribed to the suppressed interlayer induced by Hf incorporation.

The charge-trapping characteristics of Hf-doped SrTiO₃ have been studied. The thermodynamic stability of the SrTiO₃ film can be improved by Hf incorporation.  The memory device with Hf-doped SrTiO₃ as CTL displays high P/E speeds at low operating voltage and good data retention. Therefore, the Hf-doped SrTiO₃ film is a promising material as CTL for MONOS-type memory applications.

Reference

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