Phosphorene, despite its instability when directly exposed to ambient oxygen or water, has been successfully processed into stable field-effect transistors (FETs). This paper reviews the emergence and progress of phosphorene FETs, all in little over a year. In such a short time, back-gated FETs evolved into front-gated FETs, gate length was reduced to the sub-micron range, passivation by high-k dielectrics or hexagonal boron nitride was demonstrated with temporal, thermal and mechanical stability, ohmic contact was achieved down to cryogenic temperatures, and cutoff frequencies was pushed above 10 GHz. These and other attractive characteristics promise the phosphorene FET to be a viable candidate for current-generation thin-film electronics, as well as future-generation ultra-thin-body low-power-consumption high-speed and high-frequency transistors.

Table I lists chronologically the pioneering papers on phosphorene FETs, which experimentally demonstrated promising performance characteristics, despite crude construction so that the top surface of the phosphorene channel was either exposed or protected only by polymer. Additionally, although the carrier mobility, current capacity, and on/off ratio were adequate, further improvement in the subthreshold slope was needed to improve the energy efficiency of these devices. To passivate the phosphorene surface, atomic-layer deposited aluminum oxide and exfoliated hexagonal boron nitride (hBN) have been used to demonstrate phosphorene FETs that were stable under ambient conditions up to several months and over a temperature range of −263 °C to 150 °C as listed in Table II. Longer-term stability could not be assessed because phosphorene FETs exist for just little over a year.

The attractive characteristics of phosphorene FETs demonstrated to date, such as carrier mobility, current capacity, on/off ratio, cut-off frequencies, temporal, thermal and mechanical stabilities indicate that they are viable candidates for thin-film flexible electronics operating in the gigahertz frequency range. However, for higher-speed and higher-frequency applications, they need to be further improved especially in reducing the interface state density to the 1011-cm−2 range and the gate length to the 10-nm range. For such an ultrathin-body low-power consumption nano-FET, not only the gate stack, but also the entire stack from the front gate, gate insulator, phosphorene channel, back insulator, back gate, to substrate needs to be optimized together, in addition to optimization of ohmic contacts and proper scaling of all other dimensions. This daunting task may be accomplished in much shorter time than the decades it took to develop Si or III-V FETs, judging from the extremely rapid development of phosphorene FETs to date. Ultimately, the same as for all 2D devices, uniform, reproducible and large-area growth or synthesis of phosphorene will be required for low-cost high-yield manufacture.