Single walled carbon nanotubes (SWCNTs) exhibit extraordinarily high current carrying capacity and suitable band gaps for logic and thin film field-effect transistors (FETs). Progress in honing the exceptional properties of SWCNTs at the multi-tube level, however, has been dampened by incremental advances in the materials science of electronic type sorting and assembly of SWCNTs. To address these challenges we leveraged the exceptional semiconducting sorting fidelity of polyfluorene polymers and we pioneered an alignment technique known as Floating Evaporative Self-Assembly (FESA).¹ Recently, we demonstrated individually placed and uniformly pitched purely semiconducting SWCNT arrays using these techniques, allowing for negligible current lost to scaling when the arrays were implemented as the channel in FETs. The SWCNT array FETs exhibited the highest on-state conductance of 261 μS/μm with a simultaneous on/off conductance ratio exceeding 10⁵ for a multi-tube SWCNT FET.² Here we present our recent optimization of the contact resistance at the palladium-SWCNT interface, which enables a substantial increase in device on-current density compared to our previous report.

            For SWCNTs, the quality of the contact-semiconductor interface is highly dependent on the SWCNT packing density, film cleanliness, and surface energy, where any non-idealities may lead to poor palladium film adhesion, or even complete film delamination.³ To address the contact challenge we perform surface treatments on the SWCNT array prior to depositing palladium contacts, which involves rinsing the SWCNT arrays in specific solvents and annealing the films in vacuum. In XPS and optical absorbance spectra, we observe significant mass reduction of the polyfluorene wrapper while maintaining the quality and alignment of the SWCNT array. AFM height maps of the palladium contacts deposited on top of the surface treated SWCNTs demonstrate nearly ideal conformation of the palladium on the SWCNT array. The surface-treated SWCNT array FETs exhibit more than 10-fold improvement in the device on-conductance compared to non-treated samples.

[1]  Y. Joo, G. J. Brady, M. S. Arnold, and P. Gopalan,  Langmuir  30 (12), 3460 (2014).

[2]  G. J. Brady, Y. Joo, M. Y. Wu, M. J. Shea, P. Gopalan, and M. S. Arnold,  ACS Nano 8 (11), 11614 (2014).

[3]  V. Perebeinos and J. Tersoff,  Physical Review Letters 114 (8), 4 (2015).