Recently, storage market has been shifting from hard disk to SSD, and the importance of NAND flash memory, which plays a key role as a storage media in the SSD, is also increasing. Accordingly, in the manufacturing phase, the test cost of NAND flash memory is getting larger as the density of NAND flash memory is increasing. In this paper, we propose a scheme for DFT(Design for Testability) that can reduce the NAND flash test cost and apply it to the actual MBT(Monitoring Burn-in Test) manufacturing process to prove improvements in the manufacturing cost.

There are 3 steps (DC/MBT/POB) between package process and shipment.  The purpose of 3 steps is to evaluate the characteristics and to ensure the reliability. MBT equipment stresses to induce early failure of marginal devices in amount of time at hot temperature. Therefore we can reduce defective products in early stage. MBT is essential process in manufacturing NAND flash memory. Therefore, reducing MBT process cost has been a big issue. Using the characteristics of MBT application and NAND flash memory, the DFT method is devised. NAND flash memory always has bad blocks as part of the total blocks. User can not use bad blocks. Therefore it is necessary routine to manage bad blocks when devices are tested. MBT equipment consists of 48 slots and each slot has 64ea I/O channels. If a device has 8ea I/O pins, it can be tested just 8ea devices per slot concurrently. In order to test more than 8ea devices each slot, the test should be conducted in several times. This concept is called “scan”. Increasing test time is caused by increasing the total scan times in accordance with MBT structural problems. Scan and slot structure acts as a factor enabling the massive quantity test. Thus the total scan loop times take up a large portion MBT application time, we are studying ways to reduce the total scan loop times. We devised a DFT method for managing bad block efficiently. This DFT method is called multi bad block management, the details are as follows.

Previously in order to find bad blocks, MBT equipment loops scan at every single block to determine pass or fail. We suggest that the newly proposed method is storing pass/fail data of multiple blocks in NAND flash memory internal register. And it is added to the accumulator to determine pass/fail of every multiple blocks rather than single block. It is possible that scan doesn`t loop not single block but every multiple blocks. As a result, it can reduce total scan loop times as follows.

As is : (The Number of Total Blocks) x Scan Loop

To be : (The Number of Total Blocks/64) x Scan Loop

There are a large number of internals latches for pass /fail in NAND flash memory. Toggling RE(read-enable) signal outputs continuously multiple blocks Pass/Fail bit which is stored in the latch. It reduces the scan loop times of MBT, which can reduce system time. It enables test cost reduction and increases productivity due to reduced overall test time, and improves test efficiency. Status parity of 64ea blocks pass/fail parity are stored in chip for shorten the test time in MBT process. When applied to 128Gb NAND flash memory, we could reduce from 21.5 hours to 18.5 hours about 14% test time. If there are more the pass/fail latches, it can further reduce the test time. However because of the area overhead, we limit to status of 64ea blocks. With multi bad block management DFT techniques, we can reduce NAND flash memory test cost of the SSD. Also, if  applied products are developed in the future, it is expected to continue to be able to see the effect.