We have studied on the pixel-parallel 3D integrated CMOS image sensors by using embedded Au electrodes [3-5] suitable for high density integration instead of TSVs or bumps. Fig. 1(a) shows a schematic of the developed CMOS image sensor. Pixels including 128 × 96 photodiodes (PDs) and A/D convertors (ADCs) in the upper layer were connected to 16-bit counters in the lower layer for each pixel. The two functional layers were formed on silicon-on-insulator (SOI) wafers and directly bonded, mediated by Au electrodes embedded in the intermediate SiO2 layer by electroplating and chemical mechanical polishing (CMP). Each pixel size was 80 μm square with a Au electrode of 10 μm in diameter. No voids were observed at the bonded interface.
By measuring the input–output response of the developed sensor, we obtained a linear output to the light illumination intensity. The sensor also had a wide dynamic range of 96 dB, which corresponds to the 16-bit output. Signals were detected even under low illumination of 0.1 lx. Fig. 1(b) demonstrates an example of video images captured by the developed sensor. The 16-bit digital output contrast was adjusted to the standard display by compressed to 8-bit data. We confirmed the pixel-parallel operation without any pixel defects.
In summary, a 128 × 96 pixel-parallel 3D integrated CMOS image sensor with 16-bit A/D converters was successfully demonstrated by applying Au/SiO2 hybrid bonding of SOI layers. The developed process is promising for CMOS image sensors of higher performance and More-than-Moore type devices for the next generation electronics.
References
[1] J. Aoki et al., ISSCC, p.482, 2013.
[2] S. Sukegawa et al., ISSCC, p. 484, 2013.
[3] M. Goto et al., ECS trans., 61(6), p.87, 2014.
[4] M. Goto et al., IEDM, 4.2, 2014.
[5] M. Goto et al., IEEE S3S, 7c.3, 2015.