Integrated All Solid Micro-Supercapacitors Based on Bottom-up Silicon Nanostructures: From Nanomaterials to Cutting-Edge on-Chip Devices

Thursday, 2 June 2016: 10:00
Aqua 303 (Hilton San Diego Bayfront)
D. Gaboriau (CEA Grenoble - INAC-SyMMES (UGA, CEA, CNRS), SiNaPS Lab.- SP2M, UMR-E CEA/UJF), M. Brachet (IMN, CNRS/University of Nantes), D. Aradilla (CEA Grenoble - INAC-SyMMES (UGA, CEA, CNRS)), G. Bidan (INAC Dir, CEA de Grenoble), J. Le Bideau (IMN, CNRS/University of Nantes), T. Brousse (Institut des Matériaux Jean Rouxel, University of Nantes), P. Gentile (INAC-PHELIQS (UGA, CEA)), and S. Sadki (CEA Grenoble - INAC-SyMMES (UGA, CEA, CNRS))
Over the last two decades, Electrochemical Double Layer Capacitors (or EDLCs) attracted considerable attention since they bridge the gap between batteries and conventional capacitors by combining high energy and power density with an unmatched stability1. Moreover, the relative ease of miniaturization of EDLCs opens a wide horizon of applications such as autonomous sensor networks, active RFID…2

Although carbon is the most studied electrode material for micro-EDLCs, silicon remains the material of choice for “on-chip” integration, provided its surface area is sufficient to allow high capacitance values. Among the various strategies to design high surface area silicon nanostructures, the bottom-up CVD approach permits a fine tuning of the electrical and morphological parameters of the nanostructures in order to obtain the highest values of capacitance, energy and power densities, while retaining high electrode conductivity and electrochemical robustness.

EDLCs based on highly doped CVD silicon nanowires (Si-NWs)3 and nanotrees (Si-NTrs)4 were recently designed and proved extremely beneficial in terms of electrochemical window (4 V)5, maximal power densities (225 mW.cm-2) and  cyclability (>106 charge/discharge cycles). Adding branches to Si-NWs to yield Si-NTrs also largely improved capacitance values, proving the versatility and potentiality of the bottom-up approach. However, previously published work rarely studied the influence of the morphological parameters on the supercapacitive behavior of the SiNTr-based electrodes and several steps are still required to permit “on chip” integration.

In the present work, we improved previously published performances by designing advanced Si-NTrs morphologies using a simple, selective and cost effective electroless gold deposition method for the CVD catalyst deposition steps. The highly conductive Si-NTrs forests were optimized concerning “trunks” and “branches” density, length and diameters, yielding a single electrode specific capacitance value as high as 1.7 mF.cm-2with excellent cyclability and large cell voltage (using a EMI-TFSI as the electrolyte).

These optimized Si-NTrs were successfully grown on microstructured interdigitated electrodes, paving the way to future integrated all-silicon “on chip” micro-EDLC. Moreover, solid state micro-EDLC were obtained combining silicon nanotrees and  ionogel electrolyte, thus leading to highly stable, solder reflow resistant devices able to withstand exceptional temperature conditions with a quasi-ideal capacitive behavior. Finally, the electrode/electrolyte interface was drastically improved by highly conformal surface coatings, leading to extremely large electrochemical windows over 4 V, improved Coulombic efficiency and unprecedented cycling ability over tens of millions of charge/discharge without significant damages.

(1) Simon, P.; Gogotsi, Y. Nat. Mater. 2008, (11), 845-54

(2) Beidaghi, M.; Gogotsi, Y. Energy & Environ. Sci. 2014, 7 (3), 867-884

(3) Thissandier, F. et al., Nano Energy 2014, 5, 20-27

(4) Thissandier, F. et al., J. of Power Sources 2014, 269, 740-746

(5) Berton, N. et al., Electrochem. Commun. 2014, 41, 31-34