Most of the current electronic devices compose of millions of transistors that are packed into an area smaller than a fraction of a fingernail and the continuing improvement of consumer devices are driven by the miniaturization of these devices for the past four decades.  By shrinking down the sizes of these electronic components, device performances are improved such as reducing power consumption and increasing device speed, as well as other enhancements such as complex functionalities, portability and cost reduction.  This leads to the wide-spread usage of electronic devices in every aspect of society, from increasing productivity in automations in manufacturing industries to vital signs monitoring in biomedical sector.  As the channel length of silicon transistors, the work horse of modern electronic devices, shrank from few hundred micrometres to tens of nanometres, new challenges had surfaced which necessitated the development of novel device designs and fabrication techniques, such as ultrathin body (UTB) technology, high-k gate dielectrics, strained channel material and tri-gate design in FinFET.  While these advances in electronics have been instrumental in sustaining the Moore’s law for the past decade, further improvement in the coming years would require adoption of novel materials and transistor geometries.

Since the successful demonstration of thermodynamically stable two dimensional (2D) graphene by Novoselov, et al. and Berger, et al. in 2004, and the subsequent studies on the properties of graphene and other layered 2D materials, the idea of using these atomically thin layers as the channel material in field-effect devices has been investigated extensively.  A wide range of 2D materials have been proposed and studied, including graphene, transition metal dichalcogenides (TMDs), hexagonal boron nitride (h-BN) and black phosphorus (BP), as well as 2D version of traditional material such as silicene and germanene. Experimentally, most of these materials applied into FET type devices haven been demonstrated and theoretically, it has also been intensively studied their FET performance down to sub 10nm. However, the devices simulated thus far had been restricted to double gated structures, which have not been demonstrated experimentally.  Furthermore, due to the weak van der Waal (vdW) forces between the 2D material layers, the electrostatic environment of single top gate device diverges from the usual ultra-thin materials.  Therefore, in this work, using BP as the example, we firstly investigate the device performance of few-layer 2D layered material FETs with a single top gate device structure MOSFET and Schottky barrier FET. The current characteristics of the devices is obtained via a non-equilibrium Green’s function (NEGF) quantum simulator using Wannier function Hamiltonians based on first principle calculations, which enables the investigation of the individual BP layers potential profile at different gate biases.  Therefore, the effect of van der Waals interlayer interaction on device performance and carrier transport properties in multilayer BP FETs can be fully and properly studied.

 Finally, we will discuss the ultimate voltage scalability of a double-gate ultra-thin body (DG-UTB) FETs employing materials from group IV, III-V, and 2-dimensional (2D) materials, including BP, MoS₂, etc., based on International Technology Roadmap for Semiconductors (ITRS) projected specifications for high performance (HP) and low power (LP) technologies. The ballistic performance of FETs designed based on the ITRS specifications for 2018 and beyond was evaluated via the semiclassical ballistic transport model. The device performance of 2D layer materials in FET applications will be compared to devices based the conversional semiconductor materials, such as Si, Ge, InGaAs and GaSb, based on ITRS roadmap requirement and their potential applications fitted into the future needed will be also addressed to provide the guidelines for future industrial development.