In the present research work, the influence of Fin width thickness variation on the electrical performance parameters have been performed for the FinFET device. Various Fin angle (i.e., θ) have been considered to analyze the effect of Fin thickness variations. All the analyzed results have been compared with the ideal FinFET (i.e., θ = 0) device to observe the effect of angle variation on threshold voltage (V_TH), Transconductance (g_m), Gate current (I_G) and Drain Induced Barrier Lowering (DIBL). In addition, the impact of Fin width thickness variations has been used to realize the inverter Voltage Transfer Characteristics (VTC). The characteristics comparison reveals that including the effect of Fin width improves the device performance of FinFET devices.

INTRODUCTION

The FinFET device has been considered as a future candidate for VLSI circuit design and manufacturing. Compared with planar technology, the FinFET device shows reduced Short Channel Effects (SCEs) and improved electrostatic control. However, device variability poses a severe threat to downscaling FinFET dimensions in the nanoscale regime because non-uniformity has a significant influence on short-channel devices [1, 2]. In the fabrication of FinFET devices, the effect of the nonrectangular Fin shape must be carefully considered because the Fin thickness of the fabricated FinFET differs from the ideal shape. It is found that it is difficult to achieve a perfect rectangular Fin shape due to Line Edge Roughness (LER) and Line Width Roughness (LWR) [3]. In previous research works, authors considered the variations introduced in the vertical direction of the Fin while ignoring the fact that Fin width fluctuates in the lateral direction too [4]. This lateral Fin fluctuation introduces significant errors during performance parameter analysis. Therefore, this present research work focused on fluctuations in the Fin in the lateral direction. Here, the effects of non-uniformity on electrical performance parameters such as V_TH, g_m, I_G and DIBL have been analyzed and compared with the ideal FinFET device. Furthermore, the impact of these variations is incorporated into the realization of inverter VTC characteristic.

DEVICE DESIGN AND RESULT ANALYSIS

Fig. 1(a) shows the full 3D view of the FinFET device. The doping concentration of the Source/Drain (S/D) region is maintained at 1×10²⁰ cm^-3. Here, channel thickness (T_si) and gate oxide thickness (t_ox) are 8 nm and 1 nm, respectively. Titanium Nitride (TiN) metal has been employed as the gate electrode because TiN shows low resistivity, high melting, thermal stability, and compatibility with the standard CMOS process [5]. To analyze the effects of fin width variation on the performance parameters of FinFET, the non-uniformity has been shown in Fig. 1(b). Here, T_si fluctuations are approximated as a linear slope, making an angle (θ) to X-axis in the range of -7⁰ to 7⁰ to exaggerate the width variation effects. A Positive angle means the drain area is more significant compared to the source area and vice versa. Fig. 2 displays the V_TH and DIBL variations against the Fin width variation. It has been realized that for Fin thickness variation from -7⁰ to +7⁰ there is a shift in threshold voltage (V_TH) of 6.12% and 4.08%, respectively. However, it is also observed that the non-uniform Fin width improves the DIBL for the FinFET device. This is due to the modulation of the effective S/D area with the channel region.

CONCLUSIONS AND FUTURE ASPECTS

The effect of Fin width thickness variation is increasing as the feature size of the FinFET device reduces. This work realized that the linear variation in the overall Fin width thickness introduces comparable variations in electrical performance parameters for FinFET device. For instance, there is a significant improvement in DIBL for Fin thickness variation from -7⁰ to +7⁰ because these variations are directly correlated to the Fin thickness reduction. These insights will allow technologists and designers to capture a valid performance characteristic for Fin width variations effects to meet future design challenges in the nanometer regime.

REFERENCES

[1] A Khakifirooz, IEEE Trans. Elect. Dev., vol. 55(6), pp. 1401-1408, 2008.

[2] RS Rathore, IEEE 4^th International Conference on Signal Processing, Computing and Control (ISPCC), Solan, 2017, pp. 377-380.

[3] RS Rathore, Superlattices and Microstructures, vol. 113, pp. 213-227, 2018.

[4] X Wu, IEEE Trans. Elect. Dev., vol. 52(1), pp. 63-68,2005.

[5] AR Brown, IEEE Trans. Elect. Dev., vol. 54(11), pp. 3056-3063, 2007.