Invited Presentation: Logic Devices with Graphene PN Junctions

Graphene p-n junctions (GPNJs) can be configured as  logic devices that can meet the scaling challenges of CMOS devices.  In the present context, GPNJs are not rectifying diodes since graphene is gapless.  Instead, they exhibit unique angle dependent transport properties that allow the development of new type of electron-optics devices.  This angle dependence has been used to predict novel devices, including the Veselago effect, steep subthreshold slope devices, and wave guiding structures.

Here, we describe the fabrication and characterization of GPNJs.  We use buried gates to electrostatically dope the graphene to form the p- and n-doped regions.  The buried gates are fabricated in CNSE’s advanced 300mm wafer line, which is used to obtain an atomically smooth dielectric surface above the gates to preserve the intrinsic electronic structure of graphene.

Using the split gates, we study different angled GPNJs  and perform electrical measurements to extract the junction resistance.  We observe a strong angle dependent junction resistance and confirm Klein tunneling, the normal tunneling component with unity transmission. By blocking the Klein tunneling component, we observe high on/off ratio devices.