Invited Presentation: The Bilayer Pseudo-Spin Field-Effect Transistor: Overview and Quantum Transport Simulation

Monday, May 12, 2014: 10:40
Bonnet Creek Ballroom XII, Lobby Level (Hilton Orlando Bonnet Creek)
L. F. Register, X. Mou, and S. K. Banerjee (The University of Texas at Austin)
The Bilayer pseudo-Spin Field Effect Transistor (BiSFET) [1] is a novel device concept that relies on the possibility of room-temperature excitonic (electron-hole) superfluid condensation in two dielectrically-separated graphene layers [2,3] or other two-dimensional material. The BiSFET is intended to enable much lower voltage—at or below the thermal voltage kBT/q ≈ 26 mV at room temperature—and power operation than possible with Complementary Metal Oxide Semiconductor (CMOS) logic [1,2]. The current-voltage (I-V) characteristics of the proposed BiSFETs, however, are also qualitatively much different from those of MOSFETs, so that new ways to perform logic operations and other functions are both required and offered [4]. At the time of writing, the BiSFET remains a novel transistor concept based on novel physics in a novel material system. Such a room-temperature condensate has not been observed (although it is also the case that the expected necessary experimental conditions have not been realized). However, experimental results in mostly III-V semiconductor double quantum well heterostructures have exhibited much of the essential transport physics required, if only at very low temperatures and under high magnetic fields, e.g. [5]. It is the latter requirements only that the use of graphene layers is intended to eliminate [1,2,3].

In this presentation, we will provide an overview of essential BiSFET concepts, and then focus on recent work to understand better how such devices would work to understand better their potential value.  We will address both inter- and intra-layer transport within the excitonic superfluid condensate system. To this end, we have developed and performed quantum transport simulations that include the non-local interlayer Fock-exchange interaction on which condensate formation is based.

Through simulation, we exhibit the predicted transition from nearly short-circuit behavior below a critical current/voltage to nearly open circuit condition for DC interlayer current flow.  Specifically, we have found interlayer conductance of approximately three-fourths of the Landauer-Büttiker limit for perfect transmission below the critical voltage. Above the critical voltage, a spontaneous oscillatory behavior is expected instead of a steady-state current, similar to that of the AC Josephson effect but on the THz and above scale here that would be filtered out in practical circuits.  Our simulations have confirmed the lack of steady-state solutions above the critical current, and oscillations in the results from iterative calculations, consistent with this expectation.    

Through simulation, we also have confirmed that the critical voltage varies as a function of the bare/single particle interlayer coupling strength through the interlayer dielectric, and that the critical voltage can be less than the well below the thermal voltage of 26 mV at 300K.

In addition to above critical results, we will show how intra-layer biasing produces near perfect interlayer Coulomb drag. Moreover, to date, field-effect gating has been envisioned for the BiSFET, to adjust the strength of the condensate or the effective contact resistance of individual devices to adjust the critical voltage (where only a little adjustment is needed).  However, we are also pursuing the possibility of mixing inter-layer and intra-layer biasing to provide current-controlled switching in what could be called a Bilayer pseudoSpin Junction Transistor (BiSJT), which could reduce device-to-device variability and providing alternate circuit schemes.

Acknowledgment:  This work is supported by the Nanoelectronics Research Initiative (NRI) through the Southwest Academy of Nanoelectronics (SWAN). Supercomputing resources were provided by the Texas Advanced Computing Center (TACC).     

References: [1] S. K. Banerjee, L. F. Register, E. Tutuc, D. Reddy, and A. H. MacDonald,  IEEE Electron Device Lett. 30, 158–160 (2009). [2] H. Min, R. Bistritzer, J.-J. Su, and A. H. MacDonald, Phys. Rev. B 78, 121401 (2008). [3] I. Sodemann, D. Pesin, and A. MacDonald, Phys. Rev. B 85, 195136 (May 2012). [4] D. Reddy, L. F. Register, E. Tutuc, and S. K. Banerjee, IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 755–764, 2010. [5] D. Nandi, A. D. K. Finck, J. P. Eisenstein, L. N. Pfeiffer, and K. W. West, Nature, vol. 488, no. 7412, pp. 481–484, Aug. 2012.