Fabricating High-Performance Silicon Thin-Film Transistor by Meniscus Force Mediated Layer Transfer Technique
EXPERIMENTAL. The SOI layer [p-type Si(100), 10-30 W∙cm] was patterned to form a 3-µm-wide and 5-µm-long dog-bone shape with 20×20 µm2 square regions at both ends. This pattern is applicable to MOSFET fabrication to form a source, a channel, and a drain. To form supporting columns, holes with size of 2 × 2 µm2 were made at intervals of 3 µm in the square regions. The 300 nm-thick buried-oxide (BOX) layer was isotropically etched by 33% hydrofluoric acid at room temperature for 90 seconds by using the patterned SOI layer as a mask for the midair cavity. As a result of the etching of the BOX layer below the patterned SOI layer, the narrow SiO2 columns can be formed underneath both end regions of the film. Figure 1 schematically shows the meniscus force(F=πR2γ[(1/R)-(2cosθE/H)]+2πR2γsinθE) mediated layer transfer (MLT) of SOI layer to a flexible substrate. The starting and counter PET substrates were in close face-to-face contact with the filling water, and these substrates were heated on a hot plate at 80°C.
RESULTS AND DISCUSSION. When the starting SOI wafer and the PET substrate were separated, it was confirmed that the original form and position of the SOI layer were completely maintained after the film transfer. The electron-backscatter-diffraction (EBSD) pattern map confirms that a (100)-oriented c-Si thin film was successfully formed on PET substrate at 80°C. Here, to confirm the adaptability of this layer transfer technique to thin-film devices, MOSFET were fabricated on a PET substrate. The source and drain regions were implanted with phosphorus ions at a dosage of 1×1015 cm-2. To control the threshold voltage, boron ions were injected (at a dosage of 1×1011 cm-2) into the channel region. After impurities in the source, channel, and drain regions were activated by heating at 1000 ºC in nitrogen ambient for 10 minutes, the BOX layer was isotropically etched by 33% hydrofluoric acid at room temperature for 90 seconds by using the patterned SOI layer as a mask for the midair cavity. As a result of the etching of the BOX layer below the patterned SOI layer, the narrow SiO2 columns can be formed underneath both end regions of the film. Here, the key process is the thermal oxidation of the SOI layer on the midair cavity. An 11-nm-thick gate insulator was formed on a SOI wafer temperature at 1000 ºC in dry oxygen ambient for four minutes. By thermally oxidizing the SOI layer, the SOI layer can be covered on both surfaces with SiO2. After that, the forming gas annealing was performed at 400 ºC in a 3%-hydrogen/nitrogen mixture for 30 min. The thermal oxidation and subsequent hydrogen anneal ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. After the SOI layer was transferred to the PET substrate by MLT technique, a 200-nm-thick SiO2 film was deposited at 130 ºC by remote plasma chemical vapor deposition (RPCVD). After the contact holes are opened, the gate, source, and drain electrodes are formed by aluminum evaporation and wet etching. The MOSFET dimensions are length (L) of 3.7 µm and width (W) of 3 µm, and the maximum temperature of the fabrication process is 130ºC. Figure 2 shows Id-Vg characteristics of the MOSFETs fabricated on a transferred Si film. The MOSFET dimensions are L = 3.7 µm and W = 3 µm. The MOSFET showed a mobility of 343 cm2V-1s-1.
ACKNOWLEDGEMENTS.A part of this work was supported by Research Institute for Nanodevice and Bio Systems, Hiroshima University and Funding Program for Next Generation World-Leading Researchers (NEXT Program) from the Japan Society for the Promotion of Science (JSPS). This work was supported by JSPS KAKENHI Grant Number 252156.
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