Novel Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications
The combination of an ambipolar electrostatic doping back-gate (BG) configuration and a separated current flow control front-gate (FG) results in a superior on-to-off current ratio and leakage suppression at high temperatures, e.g. more than 3 decades at 700 K. This mainly results from the high front-gate barrier height of 0.57 eV (Fig. 2, 3). Depending on its polarity, the BG accumulates either holes or electrons at the interface between top silicon and buried oxide and at the same time facilitates carrier tunneling through the Schottky-barrier contacts at source/drain. In contrast, the FG can locally suppress the accumulation by the BG and control the flow of charge carriers (Fig. 2, 3).
The simulations are backed by measurements on SiNW FETs (Fig. 4). Fabrication of planar devices based on our SiNW technology and electrical measurement are consistent with simulation. Detailed results will be presented at the meeting.
So far, all ambipolar devices with a separate gate to control the current flow involve nanowire structures as, for example, silicon nanowires or carbon nanotubes. To the best of our knowledge, this is the first demonstration of a novel electrostatically doped planar field effect transistor for high temperature applications.
Furthermore, the degree of freedom to select instantly n- and p-type behavior via the polarity of the BG allows designing reconfigurable circuits with increased functionality . Additionally, as no classic doping process is required, the device does not suffer from dopant dependent reduction of carrier mobility and statistic dopant fluctuation that typically arise in modern aggressively scaled MOSFET devices.
 F. Wessely, T. Krauss, U. Schwalke, “Virtually dopant-free CMOS: midgap Schottky-barrier nanowire field-effect-transistors for high temperature applications“, Solid-State Electronics, vol. 74, pp. 91-96, 2012.