Novel Electrostatically Doped Planar Field-Effect Transistor for High Temperature Applications

The dominating leakage path for OFF-state currents in today’s downscaled MOSFET devices originate from PN-junction and bulk leakage [refs. 1, 2]. These leakage currents increase severely with temperature. SOI technologies can reduce bulk-leakage currents significantly. However, PN-junction leakage is still present even in SOI FETs. Therefore, our device concept replaces conventional source/drain PN-junctions with Schottky-barrier contacts in a dopant-free CMOS environment. This adds a high temperature robustness as reported recently for fabricated silicon nanowire (SiNW) FETs [refs. 3, 4]. We have extended the SiNW-concept to planar, non nano-wire device structures.

The combination of an ambipolar electrostatic doping back-gate (BG) configuration and a separated current flow control front-gate (FG) results in a superior on-to-off current ratio and leakage suppression at high temperatures, e.g. more than 3 decades at 700 K. This mainly results from the high front-gate barrier height of 0.57 eV (Fig. 2, 3). Depending on its polarity, the BG accumulates either holes or electrons at the interface between top silicon and buried oxide and at the same time facilitates carrier tunneling through the Schottky-barrier contacts at source/drain. In contrast, the FG can locally suppress the accumulation by the BG and control the flow of charge carriers (Fig. 2, 3).

The simulations are backed by measurements on SiNW FETs (Fig. 4). Fabrication of planar devices based on our SiNW technology and electrical measurement are consistent with simulation. Detailed results will be presented at the meeting.

So far, all ambipolar devices with a separate gate to control the current flow involve nanowire structures as, for example, silicon nanowires or carbon nanotubes. To the best of our knowledge, this is the first demonstration of a novel electrostatically doped planar field effect transistor for high temperature applications.

Furthermore, the degree of freedom to select instantly n- and p-type behavior via the polarity of the BG allows designing reconfigurable circuits with increased functionality [5]. Additionally, as no classic doping process is required, the device does not suffer from dopant dependent reduction of carrier mobility and statistic dopant fluctuation that typically arise in modern aggressively scaled MOSFET devices.

[1]     J. Appenzeller et al., “Toward nanowire electronics”, IEEE Transactions On Electron Devices, vol. 55, pp. 2827–2845, 2008.

[2]     Koo et. al, “Silicon nanowires as enhancement-mode Schottky barrier field-effect transistors”, Nanotechnology, vol. 16, pp. 1482–1485, 2005.

[3]     F. Wessely, T. Krauss, U. Schwalke, “Reconfigurable CMOS with undoped silicon nanowire midgap Schottky-barrier FETs“, Microelectronics Journal 44 (12), pp. 1072-1076, 2013.

[4]     F. Wessely, T. Krauss, U. Schwalke, “Virtually dopant-free CMOS: midgap Schottky-barrier nanowire field-effect-transistors for high temperature applications“, Solid-State Electronics, vol. 74, pp. 91-96, 2012.

[5]     J. Trommer et al., “Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors”, Electron Device Letters, vol. 35 (1), pp. 141-143, 2014.