The Study of Charge Trapping in Mahas Memory Structure with Various HfO2 Trap Layer Thicknesses

Recently, charge trap type memory devices are developed to replace the conventional floating-gate flash memories for high quality memory operation in dense memory cell array. However, memory reliability characteristic degradations have arisen from the tunnel oxide thickness scale down in the ‘ONO’ (SiO₂/Si₃N₄/SiO₂) type charge trap memory. To overcome this limitation, high-k dielectrics have been attempted by replacing the charge trap layer (CTL) SiN_x / blocking layer (BL) SiO₂. Especially, HfO₂ and Al₂O₃ have been mainly developing for CTL and BL, respectively. But, it is still required to investigate the high-k dielectrics scale down for improvement of memory performance. In this study, optimized thickness of the HfO₂ CTL was investigated in Junctionless devices with poly silicon channel. Increase Step Pulse Program (ISPP) characteristic in HfO₂ CTL device show less sensitive to thickness scale down than SiN_x CTL device. But, under the 6nm of HfO₂ thickness, ISPP slope degradation was observed by high applied voltage pulse. It is expected that amount of tunneling electron through the Al₂O₃ BL is increased by decrement of dielectric thickness. By program/erase results, 4.6nm SiN_x CTL device show poor erase characteristic comparison with HfO₂ CTL device. Consequently, very slow program and erase operation during endurance test was observed in SiN_x CTL device. For these results, we are expected that optimized HfO₂ CTL can be replaced conventional SiN_x CTL for next generation NAND flash memory.