The Study of Charge Trapping in Mahas Memory Structure with Various HfO2 Trap Layer Thicknesses

Wednesday, 8 October 2014
Expo Center, 1st Floor, Center and Right Foyers (Moon Palace Resort)
H. Na (Department of Materials Science and Engineering, Yonsei University), J. Oh, K. Lee, and H. Sohn (Department of Materials Science and engineering, Yonsei University)
Recently, charge trap type memory devices are developed to replace the conventional floating-gate flash memories for high quality memory operation in dense memory cell array. However, memory reliability characteristic degradations have arisen from the tunnel oxide thickness scale down in the ‘ONO’ (SiO2/Si3N4/SiO2) type charge trap memory. To overcome this limitation, high-k dielectrics have been attempted by replacing the charge trap layer (CTL) SiNx / blocking layer (BL) SiO2. Especially, HfO2 and Al2O3 have been mainly developing for CTL and BL, respectively. But, it is still required to investigate the high-k dielectrics scale down for improvement of memory performance. In this study, optimized thickness of the HfO2 CTL was investigated in Junctionless devices with poly silicon channel. Increase Step Pulse Program (ISPP) characteristic in HfO2 CTL device show less sensitive to thickness scale down than SiNx CTL device. But, under the 6nm of HfO2 thickness, ISPP slope degradation was observed by high applied voltage pulse. It is expected that amount of tunneling electron through the Al2O3 BL is increased by decrement of dielectric thickness. By program/erase results, 4.6nm SiNx CTL device show poor erase characteristic comparison with HfO2 CTL device. Consequently, very slow program and erase operation during endurance test was observed in SiNx CTL device. For these results, we are expected that optimized HfO2 CTL can be replaced conventional SiNx CTL for next generation NAND flash memory.