Via Superfill with Time Pulse Plating in a Dual Couple Redox System

Tuesday, 7 October 2014
Expo Center, 1st Floor, Center and Right Foyers (Moon Palace Resort)
S. Nad, Y. Sun (Substrate Packaging Technology Development, Intel Corporation), R. Chalupa (Design and Technology Services, Intel Corporation), C. Pendyala, and K. Ganesan (Substrate Packaging Technology Development, Intel Corporation)
As fine line spacing (FLS) and blind micro vias (BMV) in substrate manufacturing progressively trend towards lower pitch, finer lines and high aspect ratios, electrodeposition of copper has become more challenging in the microelectronic packaging industry. Plating processes in substrate manufacturing necessitate high current densities to meet throughput concerns resulting in a high copper depletion gradient at the surface and via fill challenges to eliminate trapped voids. We present a manufacturable solution demonstrating a defect free, single bath electrolytic plating process by utilizing an “off-time” enabled forward-reverse pulses in a coupled Fe2+/ Fe3+redox plating solution.

DC plating, modulating plating by current density variation, has been the historical norm in plating techniques employed for via fill. Time pulse plating has the added advantage in its ability to tune composition, structure and porosity by employing varied combinations of current amplitudes and time pulses.

In a normal via-fill bottom up plating process, local plating rate is proportional to the local cupric ion concentration. The bottom of the via sees lower concentration than the top of the feature leading to pinch off or void formation. We investigated fluid velocity dependent convective transport inside the via. Flow velocities for both large and small vias were found to be very low for wide range of inlet flow velocities. Peclet numbers of < 10-4indicate an overwhelming dominance of diffusion impacting ion transport in the interior of the feature.

When an “off time” step is incorporated into a pulsed plating recipe, it enables the relaxation of the cupric ion gradient inside the via feature by diffusion (unhindered by consumption along the vertical sidewall) while the presence of the Fe2+/ Fe3+redox couple enables preferential etching of the top of the via feature versus the bottom. This exaggerates the bottom-up fill effect and can be tuned to achieve super fill of the vias leading to a robust void free filling.

We demonstrate that the incorporation of an “off-time” can result in void free fill and achieve super fill conditions in high aspect ratio via features.