Dual Damascene Copper Electroplating Enabled Scaling of the Wires and Multilevel Interconnects

The invention of the copper damascene plating process by IBM in the early 1990’s was successful because it not only provided a solution to a problem but enabled the scaling of interconnects for many generations that followed. Aluminum metal had been used for the contacts as well as wiring in early transistor technology. Cobalt silicide contacts were introduced which not only gave much lower contact resistance with the implanted silicon but were self-aligned (from which the term “salicides”) as a result of a reaction between cobalt metal and the exposed silicon areas. This self-aligned reaction enabled further scaling of the contacts for the next nodes of transistors. Aluminum also had many issues for scaling of the interconnects and was effectively replaced by copper in 1997. The reason that is most commonly quoted is the modest decrease in resistivity along with the improvement in electromigration resistance at higher temperatures. The opposition to copper as wiring material was however major and the material property advantages only would probably not have tipped the scale. Remember that yield and reliability were at stake as copper is a killer impurity for MOSFET device performance. The demonstration of diffusion barriers such as Ta/TaN could not change this completely as the risks for contamination were real and preventive procedures as we know today were still untested. Another aspect which should not be underestimated, is that plating was (incorrectly) considered a dirty process by many in the vacuum process dominated world of solid-state physics and microelectronics. Hence, the introduction of copper electroplating was in many aspects revolutionary and meant a major change in silicon chip manufacturing.

What did tip the scale then? As for the silicide process, the damascene plating process simplified the interconnect manufacturing process but importantly it provided a cost-effective technology  that facilitated  further interconnect scaling. A single layer of aluminum wiring was made by a subtractive integration where the aluminum wires were masked by photoresist and dry etched. Copper, on the other hand, could be integrated by an additive approach where the copper was inlaid in preformed silica-based layers. Copper was plated in and outside the features at the same time and excess copper or overburden was removed again by chemical mechanical polishing. The dual damascene copper electroplating process meant that the vertical interconnect via-level and horizontal interconnect lines could be fabricated in one step, meaning a considerable cost reduction. The processes of dielectric deposition, dielectric patterning and etch, liner and copper seed deposition, copper electroplating and CMP can be repeated many times over building a multilevel interconnect stack. This meant that the Back-end-of-line (BEOL) materials and processes became major part of chip manufacturing process. Optimization of the plating chemistry and the dielectric materials kept the interconnect scaling roadmap going from the first 350nm copper lines in 1997 to the current 32nm copper lines in the first metal level (M1). Scaling of the copper wire cross-section also means scaling of the liner and seed thickness. Already in the late 90s, direct plating processes were being explored where the copper seed layer would no longer be required, thus providing more space in the narrow features for copper filling itself. The real challenge of direct plating lays in the combination of the terminal effect caused by the resistive liner and the nucleation and growth of copper into a coalesced film. Even though 300mm full-wafer one step direct plating has been demonstrated it is not yet used. One of the reasons is that, contrary to the relative simplicity of the conventional copper electroplating process, direct plating may be to be too difficult for a manufacturing environment. It requires a profound understanding of the direct plating process, which makes that specialists would be needed from the concept to production stages. Further, it requires a close synergy between the developments in the electrochemical process, the non-copper seed layer and the hardware. In addition, there has been no immediate need for it as the evolutionary development of PVD thin copper seed processes has kept up well with scaling demands. Further, the much easier to implement wet seed process can provide a few more nodes extension in copper plating. As such, the one-step direct plating process has missed its point of opportunity as the number of nodes that it could serve has become too limited. For the sub 22nm node, reflow of PVD copper is one of the favorite technology candidates. This shows that many factors are involved in the process from invention to application.