Electrochemical Flip-Chip Interconnect Technology

The flip-chip interconnect technology introduced to microelectronic packaging a high number of inputs/outputs (I/O), high interconnect density and most importantly improved electrical and thermal performance¹. Fabrication of PbSn solder Controlled Collapse Chip Connections (C4) by evaporation through a metal mask was pioneered by IBM^{2, 3} in the 60’s as a high reliability packaging method. However, evaporation, besides requiring a large capital investment, is typically less than 5% efficient.  More than 95 % of the evaporated material ends up on the evaporator wall and on the metal mask, which need to be cleaned, and the Pb-containing waste has to be disposed of by an expensive, regulated procedure. Both the Under-Bump-Metallurgy and the 97/3 Pb/Sn solder solder were evaporated through a molybdenum metal mask.  However, as the wafer size progressively increased and the solder dimensions decreased, the thermal mismatch between the mask (4.8 ppm/^oC) and the Si wafer (2.6ppm/^oC) limited the extendibility of the evaporation process.³ 

 The electrochemical fabrication of flip-chip solder technology is an extremely selective and efficient process which is extendible to larger wafer sizes, to finer dimensions and to higher C4 density.^{3, 4} Our focus was the development of a manufacturable technology that was based on additive and subtractive thin film processing.⁴

 A typical process flow for the fabrication of the flip-chip interconnection is as follows.  On the passivated chip, that has vias to the Cu pads, a blanket barrier layer of TiW or Cr is deposited by sputtering.  A blanket CrCu layer about is sputtered over the barrier layer. A blanket Cu seed layer is sputtered on top of the CrCu layer. The role of the CrCu is to provide improved adhesion of the solder intermetallic (typically Cu₃Sn or Cu₆Sn₅) with the underlying barrier layer. The C4 pattern is defined on the wafer with an appropriate photoresist of thickness at least as great as the thickness of the plated solder.  The solder is electroplated through the resist mask, as an alloy or as sequencial thin films. The resist is removed. The Cu and CrCu are removed by selective electroetching or chemical etching. The TiW or Cr is removed by chemical etching. The solder is treated and reflowed in an appropriate atmosphere. The wafer is diced into chips, that are joined to a carrier employing a suitable flux.

 Modeling, experimental matrices, process control and equipment were developed to enable great manufactur-ability and scalability of the flip-chip process. ^{4, 5}

 In order to meet the requirements of the European Union Restriction of Hazardous Substances (RoHS), lead-free solder alloy technologies have been developed.^{6, 7}   The lead-free solders and plating processes have begun to made their way into adjacent spaces for interconnecting solar cells.⁸

 

REFERENCES

1. N.G. Koopman, T.C. Reiley, P.A. Totta, “Chip to Package Interconnections,” R. Tummala and E. J. Rymaszewski, Editors, Microelectronics Packaging Handbook, Van Nostrand Reinhold, NY, p.361(1989).

2. R. A. Totta and R. P. Sopher,  IBM J. Research Dev., 16, 226 (1969).

3. P.A. Totta, “History of  Flip Chip and Area Array Technology,” Editors K.J. Puttlitz, P.A. Totta, Area Array Interconnection Handbook, Kluwer Academic Publications, The Netherlands, p.1-36 (2001).

4. M. Datta, R. V. Shenoy, C. Jahnes, P. C. Andricacos, J. Horkans,  J. O. Dukovic, L. T. Romankiw, J. Roeder, H. Deligianni, H. Nye, B. Agarwala, H. M. Tong, P. Totta, J. Electrochem. Soc., 142(11), J. Electrochem. Soc., 142(11), 3778- 3785 (1995).

5. US 5,516,412, “Vertical Paddle Cell,” P.C. Andricacos, K.G. Berridge, J.O. Dukovic, M. Flotta, L.T. Romankiw, K.-H. Wong, F. Spera, O. Schick, May 14, 1996.

6. US 6,224,690 B1, “Flip-Chip Interconnections using Lead-free Solders,” P.C. Andricacos, M. Datta, H. Deligianni, W.J. Horkans, S. K. Kang, K.T. Kwietniak, G.S. Mathad, S. Purushothaman, L. Shi, H.-M. Tong, May 1, 2001.

7.  S.K. Kang, D.-Y. Shi, P. Gruber, D.W. Henderson, K.J. Puttlitz,  IBM J. Research and Develop., 49(4/5), 606-620 (2005).

8. P.C. Hsiao and A. Lennon, J. Electrochem. Soc., 160(10), D446-452 (2013).