W. P. Dow (National Chung Hsing University)
Electronic products, such as computers, smart phones, laptops and so on, need chips to perform their functions. These chips have many devices, which need to be integrated and connected with each other. To expand the functions of electronic products, more MOS have not met the requirement yet compared with more chips. Therefore, the concept of three-dimensional (3D) chip stacking packaging is proposed. To meet high density interconnection (HDI), through silicon vias (TSVs), through glass vias (TGVs) used as conducting channels of chip stacking need to be fully filled with metal (e.g., copper or nickel-tungsten alloy), and microvia and through hole designed in IC packaging substrates and printed circuit boards (PCBs) need to be fully filled with copper as well. These filling plating technologies have similar process steps but their feature size is totally different.
1-11 Herein, we will review these process steps and propose novel filling plating process steps and technologies, including highly selective microvia filling without copper deposition on the outside plane surface, direct through hole filling without usage of a conducting template, TSV filling using CoWP as a barrier layer and electroless copper as a seed layer, TSV filling using reduced graphene oxide (rGO) as barrier and seed layers, TSV filling without copper but rGO combining with NiW alloy, TGV filling using electroless copper as a seed layer and direct pattern copper electroplating onto a glass wafer by using Al-doped ZnO (AZO) as an adhesive and conducting layer.
References:
1. W.-P. Dow and H.-H. Chen, Circuit World 30 (3), 33-36 (2004).
2. W.-P. Dow, H.-S. Huang, M.-Y. Yen and H.-C. Huang, Journal of The Electrochemical Society 152 (6), C425-C434 (2005).
3. W.-P. Dow, M.-Y. Yen, W.-B. Lin and S.-W. Ho, Journal of The Electrochemical Society 152 (11), C769-C775 (2005).
4. W.-P. Dow, H.-H. Chen, M.-Y. Yen, W.-H. Chen, K.-H. Hsu, P.-Y. Chuang, H. Ishizuka, N. Sakagawa and R. Kimizuka, Journal of The Electrochemical Society 155 (12), D750-D757 (2008).
5. W.-P. Dow, M.-Y. Yen, S.-Z. Liao, Y.-D. Chiu and H.-C. Huang, Electrochimica Acta 53 (28), 8228-8237 (2008).
6. W.-P. Dow, Y.-D. Chiu and M.-Y. Yen, Journal of The Electrochemical Society 156 (4), D155-D167 (2009).
7. W.-P. Dow, C.-C. Li, Y.-C. Su, S.-P. Shen, C.-C. Huang, C. Lee, B. Hsu and S. Hsu, Electrochimica Acta 54 (24), 5894-5901 (2009).
8. W.-P. Dow, C.-W. Lu, J.-Y. Lin and F.-C. Hsu, Electrochemical and Solid-State Letters 14 (6), D63-D67 (2011).
9. Y.-T. Lin, M.-L. Wang, C.-F. Hsu, W.-P. Dow, S.-M. Lin and J.-J. Yang, Journal of The Electrochemical Society 160 (12), D3149-D3153 (2013).
10. S.-P. Shen, W.-H. Chen, W.-P. Dow, T. Kamitamari, E. Cheng, J.-Y. Lin and W.-C. Chang, Microelectronic Engineering 105, 25-30 (2013).
11. J.-J. Yan, L.-C. Chang, C.-W. Lu and W.-P. Dow, Electrochimica Acta 109 (0), 1-12 (2013).
