(Invited) Comparative Simulation Study of InAs/Si and All-III-V Hetero Tunnel FETs

The Tunnel Field Effect Transistor (TFET) which utilizes the band-to-band-tunneling (BTBT) generation current of a gated diode is regarded as promising candidate for ultra-low power circuits. TFETs with different geometries and operation modes have been proposed. In this work, we study different hetero-structure systems - InAs/Si and all-III-V (In_0.53Ga_0.47As/InP, InAs/GaSb) - and compare their performance in TFET applications. First, we evaluate the TCAD model by simulating realistic structures as the one shown in Fig. 1 and compare the results with measured current-voltage (IV) characteristics. Then we focus on 2D double-gate TFETs with gate-overlapped-source geometry (Fig. 2) which capture the essential physics.

The TEM image of an InAs/Si nanowire p-TFET fabricated at IBM Research-Zurich is shown in Fig. 1. The n-doped InAs source (N_D=2e18cm^-3) is overlapped with the gate to increase “line” (under-the-gate) tunneling. Geometry and doping profile of a p-TFET used for the simulations are displayed in Fig. 2(a). The source donor concentration is at its optimum for minimum sub-threshold swing (SS), the corresponding value for the In_0.53Ga_0.47As/InP  p-TFET being N_D=1e19cm^-3. The distributions of the electron and hole BTBT generation rates in the sub-threshold regime are shown in Fig. 2(b) and Fig. 2(c) for both material systems. One observes that BTBT takes place along the line tunnel path in the In_0.53Ga_0.47As/InP TFET while it occurs primarily along a “point” tunnel path (in-junction, inter-material) in the InAs/Si TFET. This is a result of the opposite signs of the valence band offset in the two hetero-systems. The different dominant tunnel paths result in different transfer characteristics as shown in Fig. 3. In bulk-like devices, the point tunneling rate is expected to change less rapidly than the line tunneling rate. Hence, the SS (averaged over 3 decades above 1e-9A/µm) of the InGaAs/InP TFET is slightly smaller than that of the InAs/Si TFET (47.3 vs 48.5). The difference is more pronounced in n-channel TFETs formed with the same set of hetero-systems. Also the current I₆₀ (I_D@ SS=60mV/dec) is comparable (6e-9A/µm vs 2e-9A/µm). In the simulations, the effect of the diffusion barrier of the InGaAs/InP hetero-system has been minimized by a proper composition gradient.

In addition to the above effects, the quality of the interfaces will affect the IV characteristics. The lattice-matched In_0.53Ga_0.47As/InP interface is expected to exhibit a lower trap density than the highly mismatched InAs/Si interface. We will demonstrate the effect of trap-assisted tunneling on the TFET performance.