Device Physics - I

Wednesday, 27 May 2015: 08:45-11:00
Williford Room B (Hilton Chicago)
Chairs:
Yasuhisa Omura and Francisco Gamiz
08:45
Introductory Remarks
08:50
1334
(Invited) Comparative Simulation Study of InAs/Si and All-III-V Hetero Tunnel FETs
A. Schenk, S. Sant (Swiss Federal Institute of Technology), K. Moselund, and H. Riel (IBM Research-Zurich)
09:20
1335
Compact Model for Nano-Wire Tunnel Field-Effect Transistor
S. Sato, Y. Omura (Kansai University, Dept. Electronics), and A. Mallik (University of Calcutta, Dept. Electronic Science)
09:40
1336
Study of Hysteresis in Vertical Ge-Source Heterojunction Tunnel-FETs at Low Temperature
F. S. Neves (Imec, University of Sao Paulo), P. G. D. Agopian, J. A. Martino (University of Sao Paulo), A. Vandooren, R. Rooyackers, E. Simoen, A. Thean (Imec), and C. Claeys (KU Leuven, Imec)
10:00
1337
Vertical Nanowire TFET Diameter Influence on Intrinsic Voltage Gain for Different Inversion Conditions
V. D. B. Sivieri, C. C. M. Bordallo, P. G. D. Agopian, J. A. Martino (University of Sao Paulo), R. Rooyackers, A. Vandooren (Imec), E. Simoen (imec), A. Thean (Imec), and C. Claeys (KU Leuven, Imec)
10:20
1338
Analytically Modeling the Asymmetric Double Gate Tunnel FET
H. Lv (Kansai University), S. Sato, Y. Omura (Kansai University, Dept. Electronics), and A. Mallik (University of Calcutta, Dept. Electronic Science)
10:40
Break-3
See more of: H01: Advanced CMOS-Compatible Semiconductor Devices 17
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