Study of Hysteresis in Vertical Ge-Source Heterojunction Tunnel-FETs at Low Temperature

Wednesday, 27 May 2015: 09:40
Williford Room B (Hilton Chicago)
F. S. Neves (Imec, University of Sao Paulo), P. G. D. Agopian, J. A. Martino (University of Sao Paulo), A. Vandooren, R. Rooyackers, E. Simoen, A. Thean (Imec), and C. Claeys (KU Leuven, Imec)
Tunnel Field-Effect transistors (TFETs) are promising successors of MOSFETs in future low-power technology nodes, where the carrier injection is based on gate controlled band-to-band tunneling (BTBT) instead of the drift-diffusion as in conventional MOSFETs, leading to low leakage current and low power dissipation (1-2). Another advantage of TFETs is that due to the built-in tunnel barrier, their subthreshold swing (SS) is not limited by ln(10).k.T/q and can reach values smaller than 60mV/dec at room temperature (1-2).

The major concern of TFETs is the influence of defects at the channel-gate dielectric interface, in the gate dielectric and in the semiconductor channel, which can lead to trap-assisted tunneling (TAT) and degrade the device SS and performance.

In this work, an experimental study of the hysteresis in the IDS-VGS behavior of TFETs with different HfO2 thicknesses has been performed. The influence of low temperature on the hysteresis was also analyzed.

The studied devices are vertical gate all-around tunnel field-effect transistors (TFETs). These devices were fabricated at imec, Belgium, according to the flow described in (3) (figure 1).

Two process conditions were used with different thicknesses of HfO2 in the gate stack, i.e., 2nm and 3nm, deposited on top of 1nm SiO2 and followed by 5nm TiN and 30nm amorphous Si.

A 15nm-thick in-situ boron doped crystalline Ge (c-Ge) source was grown by selective epitaxy to form a Si-Ge heterojunction at the channel-source interface (3).

Plotting the drain current (IDS) at room temperature as function of the gate voltage (VGS) for the TFETs with different thicknesses of HfO2 (figure 2), one can observe that the device with the thinner HfO2 (2nm) presents a slightly higher on-current (ION) and a steeper SS. This can be attributed to the better gate-to-channel electrostatic control, due to the reduction of the tunneling path at the source/channel region by increasing the electric field (4-5).

In order to study the influence of the oxide trap density (NOT) on the TFET behavior, double sweep curves have been recorded as a function of VGS (figure 3) for a TFET with 3nm and 2nm of HfO2 and temperatures ranging from 300K to 78K.

Since at low temperature the influence of TAT and SRH carrier generation is minimized, the BTBT prevails over other mechanisms, resulting in lower SS values upon cooling. Since high interface (6) and oxide trap densities prevent the SS to reach values below the theoretical limit, their detailed study becomes necessary.

For VGS higher than 1.3V, the drain current (IDS) is dominated by BTBT, as confirmed by the extracted activation energy, and as expected presents a weak dependence on temperature variation, showing a slight decrease for the lowest temperature. At lower electric field (VGS<1.3V) the TAT is the predominant conduction mechanism, which is strongly temperature dependent, resulting in a relatively high decrease of IDS with the temperature reduction.

Focusing on the hysteresis, it is possible to observe that while the device with a thinner HfO2 does not show hysteresis in the whole temperature range, devices with 3nm HfO2 present hysteresis, which increases with decreasing temperature. The hysteresis occurs because when the gate voltage sweep up is performed, the traps in the oxide become charged by electrons injected in the gate, whereas, when the sweep down is performed, the IDS curves are shifted due to the discharge of the traps in the oxide, resulting in a relaxation of the flat band voltage to its original value.

The oxide defects are generally slow-state-traps, which are sensitive to temperature at low fields and their density tends to decrease upon heating (7), resulting in a DVGS increase at low temperature. The values of DVGS are summarized in table 1 together with the extracted NOT values at different temperatures.

Observing the IDS x 1/T for VGS=0.5V (figure 4), the influence of TAT decreases when the temperature decreases, while the hysteresis increases. This can suggest that there is no important relation between the oxide traps and TAT.

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(2) T. Krishnamohan et al., Tech. Dig. IEDM2008, 947-950, (2008).

(3) R. Rooyackers et al., Tech. Dig. IEDM2013, 4, 2, (2012).

(4) A. S. Verhulst et al., J. Appl. Phys., 104, 6, (2008).

(5) D. Leonelli et al., Solid-State Electronics, 65-66, 28-32, (2011).

(6) F. S. Neves et al., EuroSOI2013, 1, 1-2, (2013).

(7) J.-Y. Rosaye et al., Journal of Electron Devices, 1, 1-6, (2003).