Analytically Modeling the Asymmetric Double Gate Tunnel FET

This paper proposes an analytical model for the asymmetric double-gate (ADG) TFET operation.  Two-dimensional Poisson equation is solved based on the depletion approximation [1,2].  The two-dimensional potential function is given by appropriate boundary conditions.  Internal electric field is calculated from the potential model and tunnel current is numerically calculated using the Kane’s tunnel current generation model [3,4].  We used the commercial TCAD simulator in order to examine the analytical model [5].

Schematic of ADG-TFET device structure is shown in Fig. 1.  It is assumed that p-type source and n-type drain regions are highly doped.  Channel region is a p-type with the doping level of N_a.  t_ox denotes the gate oxide thickness and t_si denotes the semiconductor film thickness.  Hereafter, we call the top gate “front gate” and the bottom gate “back gate”.

Potential profile of the channel region is derived from the following two-dimensional Poisson equation based on the depletion approximation.

Equation    (1)

where q denotes the elemental charge and ε_si denotes the permittivity of semiconductor.  Here, we assume the following potential function with the cubic function of coordinate y [1].

Equation    (2)

where four factors a(x), b(x), c(x), and d(x) are functions of coordinate x.  We introduce the following boundary conditions for the potential in solving eq. (1).

 Equation    (3)

where ψ_f(x) and ψ_b(x) stand for front and back surface potentials at y=0 and y=t_si, respectively.  V_fg,fb and V_bg,fb are the front-gate and the back-gate flat-band voltages, respectively.  V_fg and V_bg are the front- and back-gate voltages, respectively.  ε_ox is the permittivity of gate insulator.

Drain current of ADG TFET is numerically calculated by integrating carriers tunneling from the valence band of the source region to the conduction band of the channel region.  We can calculate the drain current (I_DS) using the carrier generation rate (G) due to the band-to-band tunnel process.

 Equation     (4)

where we use the Kane’s model for the carrier generation rate (G) [3,4].

Equation      (5)

where |E| (=(E_x²+E_y²)^1/2) is the electric field strength, A and B are constants given by
Equation               (Si)

Equation               (Ge)

We perform the TCAD simulation [5] in order to examine the validity of the analytical model.  In device simulations for Si-based TFETs, we assume the gate material with the work function of 4.1 eV for the front- and the back-gate electrodes.

Figure 2 shows the calculated potential profiles at y=0nm, 2.5nm, and 5.0nm for t_si=10nm.  Using the potential function revealed in Fig. 2, local electric field values are calculated along with the x direction and the y direction separately.  The potential function analytically given and resulting electric fields successfully reproduced those given by TCAD simulations (not shown here).  We found a slight difference of potential profile near the surface around the source junction for a relatively low-doping source region because of the depletion in the source region [6]. We also calculated drain current characteristics.  Figure 3 demonstrates I_D-V_fg characteristics for t_si=10nm and 20nm, where the condition of L_g>2t_s is satisfied.  In Fig. 5, the model basically reproduces the TCAD result.  On the other hand, the model doesn’t well reproduce TCAD-based I_D-V_gf characteristics for t_si=30nm and 100nm (not shown here), where L_g<2t_si.  This difference stems from the linear approximation of the in-depth electric field in the model.  As the condition of L_g>2t_si is important in the future, this is not a crucial issue of the model.  In addition, we confirmed the model proposed here is available for Ge-based TFET (not shown here).

 References

[1] J.-W. Han, C.-J. Kim, and Y.-K. Choi, “Universal potential model in tied and separated double gate mosfets with consideration of symmetric and asymmetric structure,” IEEE Trans. Electron Devices, Vol. 55, pp. 1472-1479, 2008.

[2] K. Suzuki and T. Sugii, “Analytical model for n+ -p+ double-gate SOI MOSFETs,” IEEE Trans. Electron Devices, Vol. 42, pp. 1940-1948, 1995.

[3] E. O. Kane, “Zener tunneling in semiconductors,” J. Phys. Chem. Solids, Vol. 12, pp. 181-188, 1960.

[4] E. O. Kane, “Theory of tunneling,” J. Appl. Phys, Vol. 32, pp. 83-91, 1961.

[5] Sentaurus TCAD Manual ver.G-2012.06.

[6] F. Villani, E. Gnani, A. Gnani, S. Reggiani, and G. Baccarani, “A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs”, Tech. Dig., 44th ESSDERC (Venice, 2014), pp. 262-265.