(Invited) Challenges to Nano-Scale Device World

The historic trend in micro/nano-electronics these last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition, and to develop many novel functionalities for future electronic systems. We are facing today dramatic challenges for More Moore and More than more applications: substantial increase of energy consumption and heating which can jeopardize future IC integration and performance, reduced performance due to limitation in traditional high conductivity metal/low k dielectric interconnects, limit of optical lithography, heterogeneous integration of new functionalities for futures nanosystems, etc. [1-16].

Therefore many breakthroughs, disruptive technologies, novel materials, and innovative devices are needed in the next two decades.

With respect to the substantial reduction of the static and dynamic power of future high performance/ultra low power terascale integration and autonomous nanosystems, new materials and novel device architectures are mandatory for ultimate CMOS and beyond-CMOS eras, as well as new circuit design techniques, architectures and embedded softwares.

Alternative memories, especially PCRAM, RRAM or MRAM will be useful for pushing the limit of integration and performance beyond to those afforded by present Non-Volatile, DRAM and SRAM memories.

In the interconnect area, optical and RF interconnects, carbon or other 2D materials  can overcome the present limitations of copper interconnects.

Concerning ultimate processing technologies, EUV lithography, immersion multiple patterning, multi ebeam maskless or imprint lithography, as well as self-assembly of nanodevices could be used for different applications.

Future autonomous nanosystems will also need the development of nanoscale high performance novel functionalities, which could be integrated on CMOS platforms.  In this respect, nanostructures and nanodevices, especially nanowires, are of great interest for instance for improving the sensitivity, resolution, selectivity, energy consumption and response time of nanosensors, and for solar, mechanical and thermal energy harvesting.

Parallel or sequential processes could be used for the integration of these future high performance sustainable, secure, ubiquitous and pervasive systems, which will be of high added value for many applications in the field of detection and communication of health problems, environment quality and security, secure transport, building and industrial monitoring, entertainment, education, etc.

The talk will focus on the main trends, challenges, limits and possible solutions for future high performance and ultralow power nanoscale devices in the CMOS and Beyond CMOS arena, including ultra-thin films, multi-gates, nanowires and small slope switches.

References

1. F. Balestra, Nanoscale CMOS: Innovative Materials, Modeling and Characterization,               Francis Balestra Ed.,

ISTE-Wiley, 2010

2. F. Balestra, Beyond CMOS Nanodevices (Vol. 1 and 2), Francis Balestra Ed., ISTE-Wiley, 2014

3. F. Balestra et al, IEEE Electron Device Letters EDL-8, p. 410, 1987

4. C. Hu et al, VLSI 2008, p. 14

5. M. Luisier et al, IEEE EDL 30, p. 602, 2009

6. F. Conzatti et al, IEDM 2011, p. 95

7. G. Dewey et al, IEDM 2011, p. 785

8. J. Appenzeller et al, Phys. Rev. Lett. 93, 196805, 2004

9. F. Padilla et al, IEDM 2008, p. 171

10. K. Boucart et al, ESSDERC 2009, p. 452

11. F. Mayer et al, IEDM 2008, p. 16

12. D. Esseni et al, IEEE TED 60, p. 2802, 2013

13. S. Brocard et al, IEDM 2013, p. 5.4.1

14. M.H. Lee, IEDM 2013, p. 104

15. S. Brocard et al, IEEE-EDL 2, p. 184, 2014

16. M. Pala et al, J. Elec. Dev. Soc., 2014.

Acknowledgements:

The author would like to thank the Sinano Institute Members and Partners of Nanosil and Nanofunction FP7 European Networks of Excellence.