III-V Tri-Gate Quantum-Well Mosfet for 10nm Technology and Beyond

With sub-10nm node technology approaching fast, counteracting short channel effects (SCEs), sub-threshold conduction, reducing transistor off-current and gate leakage current have become aspects of real concern. Integration of III-V semiconductors in multigate device architectures has become a topic of intense research and study for low power logic implementation [1]. Multigate device architectures like FinFETs, GAA FETs provide better control over channel carrier accumulation and improved short channel performance over planar structures. Recently, In_0.53GA_0.47As Quantum-Well (QW) Tri-Gate MOSFET with bi-layer high-k dielectrics of Al₂O₃/HfO₂ has been reported with channel width and height scaled down to 30nm and 20nm respectively and gate length scaled down to 60nm [2].

In this work, we present a simulation study of inversion Capacitance-Voltage (C-V) and Threshold (V_TH) characteristics of a III-V tri-gate device (Fig.1 inset) using self-consistent modeling. The device structure used for modeling in this study incorporates 2nm Al₂O₃ with In composition kept at 0.7 in the undoped InGaAs QW channel. The In_0.52Al_0.48As back barrier thickness is kept at 60nm. In this study TiN has been used as the gate metal. In all these studies, temperature is considered to be fixed at 300K.

Finite Element Method (FEM) has been used to solve Schrodinger-Poisson equations in a coupled manner applying proper boundary conditions, using COMSOL Multiphysics and MATLAB, taking into account wave function penetration and other quantum mechanical effects. 2D Schrodinger equation is solved using effective mass approximation and open boundary condition to determine electron wave functions and eigen states in the quantum well. Using carrier wave functions in the tri-gate channel, inversion carrier concentration is determined by applying 1D density of states and Fermi-Dirac distribution function. The effect of fixed oxide charges, interface trap charges and oxide border trap charges is not taken into account. The developed simulator is also benchmarked with the simulation results obtained for a III-V GAA nanowire transistor [3]. A quantum definition of threshold voltage for multigate FETs is available in literature [4]. According to this definition, the threshold voltage can be presented as a combination of classical and quantum terms. Here, peak electron concentration n_peak(x,y) and average electron concentration n_avg are used to define threshold voltage of the device. At threshold point, the profile of n_peak(x,y)/n_avg would show a change in slope which results from shift in carrier accumulation as device operation moves from subthreshold to inversion mode [4]. In this study, same definition of threshold voltage has been used.

The simulation reveals strong carrier accumulation at the corners of the oxide/semiconductor interface which is expected for multigate device structures (Fig. 1). The simulation also reveals strong subband quantization in the QW channel (Fig. 2). Occupied subbands below the Fermi level contribute to the carrier concentration.  As the device dimension is shrunk, volume inversion effect becomes more and more significant and carriers begin to accumulate at the middle portion of the tri-gate channel. This phenomenon leads to an increase in carrier concentration in the middle portion of the QW fin as channel dimension is scaled (Fig. 3). This phenomenon shifts channel formation towards the middle portion of the tri-gate QW fin. Simulation also reveals higher inversion capacitance at lower In composition in the channel which may be attributed to higher density of states effective mass at lower In composition (Fig. 4). Although variation of top gate oxide thickness reveals effect on inversion capacitance, the threshold voltage remains mostly unchanged with top gate oxide thickness. Study of variable channel dimension while keeping W_Fin=H_Fin reveals lower carrier accumulation in the device cross section per unit channel length which may lead to lower inversion capacitance with lower channel dimension (Fig. 5). Lowering channel dimension results in stronger quantum confinement and subband splitting which eventually leads to an increase in threshold voltage (Fig. 6). Lowered In composition in the channel also increases threshold voltage of the device (Fig. 6).  

In this work, a simulation study of a III-V tri-gate quantum well device for 10nm technology and beyond is presented. The outcome of this work would be useful in the implementation of III-V multigate device structures for high speed and low power logic applications.

References

[1] R. -H. Baek et al., VLSI Tech. Dig. (2014)

[2] T. -W. Kim et al., IEDM Tech. Dig. 425 (2013)

[3] Quazi D.M. Khosru et al., ECS Transactions 169(2013)

[4] Se Re Na Yun et al., SOI Conference 137(2007)