Geometrical Magnetoresistance in Multi-Gate FDSOI Structures

Mobility characterization is very challenging on SOI multi-gate transistors where several channels coexist and interact [1-3]. Among all mobility determination procedures, only the geometrical magnetoresistance yields accurate values free of any assumption (channel length, oxide and film thickness, doping, strain, etc). 

     Magnetoresistance is a direct consequence of carrier deflection by a magnetic field. When carriers do not follow the shortest path from source to drain, the channel resistance increases. The relation between the resistances obtained when the magnetic field is present or not yields:

            R_B = R₀ ( 1 + μ_MR² B² )

     The carrier deviation by the Lorentz force is shown in Fig. 1a. The deviation is modulated by the device geometry. If the transistor is long and narrow (W/L  < 1) the Hall field opposes to the Lorentz force and the magnetoresistance is weak. However, when the sample is wide and short (W/L  >> 1) the Hall field is short-circuited by the end contacts and the Lorentz force is not compensated. Hence, carriers are deviated and the magnetoresistance is maximum. Fig. 2 illustrates the simulated electron mobility against the aspect ratio (W/L) for several magnetic field orientations. The magnetoresistance is much higher for normal magnetic fields (and W/L > 5) than for transversal fields as fully documented by experimental data [4].

     On the other hand, in double-gate FinFETs (Fig. 1b), the magnetoresistance is high even in narrow samples (W ~ L). This surprising result was explained by the lateral gate action which cancels the Hall voltage so preventing the compensation of the Lorentz force and resulting in the magnetoresistance [4].

     TCAD numerical simulations [5] were carried out to clarify the carrier deflection and magnetoresistance mobility in FinFETs. The impact of the device architecture, thicknesses, gate biasing scheme, and magnetic field orientation is documented and explained.

     References

[1] S. Cristoloveanu and S. S. Li, Electrical characterization of silicon-on-insulator materials and devices, Kluwer Academic Publishers, 1995.
[2] L. Pham-Nguyen, C. Fenouillet-Beranger, A. Vandooren, T. Skotnicki, G. Ghibaudo and S. Cristoloveanu, “In-situ comparison of Si/High-K and Si/SiO₂ channels properties in SOI MOSFETs,” IEEE Electron Device Letts., vol. 30 (10), pp. 1075-1077, 2004.
[3] F. Dauge, J. Pretet, S. Cristoloveanu, A. Vandooren, L. Mathew, J. Jomaah and B.-Y. Nguyen, “Coupling effects and channels separation in FinFETs,” Solid-State Electron., vol. 48, pp. 535-542, 2004.
[4] S.-J. Chang, M. Bawedin and S. Cristoloveanu, “Mobility Investigation by Geometrical Magnetoresistance in Fully Depleted MOSFETs and FinFETs,” Electron Devices, IEEE Transactions on , vol.61(6), pp.1979-1986, 2014.
[5] Synopsys TCAD, Sentaurus Workbench Advanced, Version H-2013.10, Synopsys, Inc.