Porous SiC/Graphene-on-Wafer Electrodes for Supercapacitors

Wednesday, 27 May 2015
Salon C (Hilton Chicago)
M. Ahmed (Griffith University), M. Khawaja (Electrical Engineering Dept, University of South Florida), M. Notarianni (Queensland University of Technology, Electrical Engineering Dept, University of South Florida), B. Wang, D. Goding (Griffith University), B. Gupta (Queensland University of Technology), J. J. Boeckl (Wright-Patterson AFB, Air Force Research Laboratory), A. Takshi (Electrical Engineering Dept, University of South Florida), N. Motta (Queensland University of Technology), S. E. Saddow (University of South Florida), and F. Iacopi (Griffith University)
The intensive research on epitaxial 3C SiC/Si wafers has opened up a new era for the micro-fabrication industry and led to the direct growth of high quality and large area graphene layers on the device location for on-chip applications.[1] This new technology to grow graphene on silicon possesses various advantages over the conventional methodology, such as eliminating the complex and unreliable process of transferring graphene flakes and replacing expensive SiC wafers, and also prompts the use of graphene for energy storage, e.g. as supercapacitors, at wafer level. However, morphology control of the graphene layers on silicon remains a challenge to further enhance the performance of supercapacitors, which mainly relies on the surface area of the active graphene layers through an electrochemical double layer mechanism. To address this issue, we demonstrate, for the first time, creating porosity on the graphene surface. The growth of porous graphene on wafers in our work presents a facile, highly reproducible and low-cost approach to obtain highly continuous graphene layers with extremely low sheet resistance. Our preliminary electrochemical investigation indicates that the porous SiC/graphene-on-wafer electrode can deliver typical supercapacitive behaviours and the porosity we create on the graphene surface can facilitate the electrochemical performance by providing more accessible surface area. Graphene prepared via this routine can also be employed to fabricate micro-supercapacitors in an interdiginated pattern for future on-chip integration and energy storage.

[1] B.V. Cunning, M. Ahmed, N. Mishra, A.R. Kermany, B. Wood, F. Iacopi, Nanotechnology, 25 (2014) 325301.