Using Graphene As a Conducting Layer and Barrier Layer for High Aspect Ratio through Silicon Via Filling

Traditional process for TSV fabrication is a dry process that includes the following step: (1) formation of vias by reactive ion etching; (2) formation of a SiO₂ isolation liner; (3) deposition of a TiN barrier layer and a copper seed layer; (4) via fill with copper electrodepositing. Herein, we attempt to use graphene to substitute the TiN barrier layer and the copper seed layer for reducing the traditional process procedure.

Graphene materials, including single layer and multi-layer graphene platelet, have recently drawn extensive attention due to their outstanding electrical and thermal properties. Reduction of graphene oxide (GO) is a method to prepare the graphene film. Since GO has a large amount of oxygen functional groups, it can be well dispersed in several solvents and enable it to be coated on a substrate by a chemical grafting method using a wet process.

In TSV technology, the thermo-mechanical fatigue may lead to failure in the TSV interconnects   because the coefficient of thermal expansion (CTE) of copper is much higher than that of silicon. The packaging materials with different CTEs will induce large stresses at interfaces. To overcome this problem, we choose graphene sheets to substitute the copper seed layer since the CTE of graphene is closer to silicon than copper. In our research, we reduce the procedure of TSV fabrication using a wet process to simultaneously substitute barrier and seed layer with graphene, and to replace filled copper with filled nickel-tungsten alloy in high aspect ratio TSV. This replacement can result in lower fabrication cost compared with the traditional TSV process.