Low Temperature Atomically Flattening of Si Surface of Shallow Trench Isolation Pattern
Figs 1(a)-1(c) show atomic force spectroscopy (AFM) images of the Si surface of large active region (p-well, 500mm × 600mm), where (a) the controlled sample (without Ar annealing), (b) the sample with Ar annealing at 900 ºC and that at (c) 850 ºC are shown. The images were obtained just after the atomic flattening Ar annealing which was applied to the samples having STI pattern. Atomically flat Si surface was successfully obtained for 850 ºC annealing, while that was not obtained for 900 ºC annealing. The results suggest that, in the case of 900 ºC annealing, O2 and/or H2O were emitted from the SiO2 film and reacted with Si surface, degrading flattening effect. The results suggested the importance of lowering of annealing temperature to obtain atomically flat Si surface when SiO2 film exists on the wafer. Relatively smaller active areas with a size of 1.26mm × 3.03mm were also measured. Figs 2(a) – 2(c) shows bird’s eye views of isolation patterns obtained by AFM for (a) the controlled sample, (b) the sample with Ar annealing at 900 ºC and that at (c) 850 ºC. Also, Figs 2(d) – 2(f) shows the AFM images of Si surface of the inside of these active areas for (d) the controlled sample, (e) the sample with Ar annealing at 900 ºC and that at (f) 850 ºC. It was found from bird’s eye’s views that the shape anomaly at the active edge was not observed, demonstrating the advantage of the low temperature annealing which can suppress reaction between Si and isolation SiO2film. Furthermore, in the case of 850 ºC annealing, atomically flat surface could be obtained. The surface roughness at the atomic terrace was the same level as the noise level (approximately 0.04 nm), while that was 0.07 nm for 900 ºC annealing and 0.13 nm for the controlled sample. The results demonstrated that the proposed low temperature and high purity atomically flattening Ar annealing is applicable to the existing CMOS process.
 S.Takagi et al., IEEE Trans. Electron Devices, 41 (1994) 2357.
 C. H. Lee et al., Tech. Dig., IEDM (2013) 13-32.
 R. Kuroda et al., IEEE Trans. Electron Devices, 56 (2009) 291.
 T. Goto et al., Extended Abstracts of SSDM2014 (2014) 670.
 Y. Matsushita et al., ECS Trans. 3 (2006) 159.
 R. Tromp et al., Phys. Rev. Lett. 55 (1985) 2332.