Investigating the Effects of Annealing on Off-State Step-Stressed AlGaN/GaN High Electron Mobility Transistors

Monday, 25 May 2015: 11:40
Conference Room 4C (Hilton Chicago)
B. J. Kim, S. Ahn, Y. H. Hwang, F. Ren, and S. J. Pearton (University of Florida)
AlGaN/GaN High Electron Mobility Transistors (HEMTs) have shown great promises for high frequency and high power applications. However, there remain some undesired issues such as electron trapping at surface states of AlGaN/GaN HEMTs, which affect the breakdown voltage, gate leakage current and current collapse.  These issues hamper the advancement of AlGaN/GaN high power and high frequency device technology and have not been fully understood. Therefore, understanding and control of trap-related effects is very important to improve the performance of AlGaN/GaN HEMTs. Recently, post-process annealing has been widely employed to increase the performance of AlGaN/GaN HEMTs. In this work, the effects of annealing on off-state drain-voltage step-stressed AlGaN/GaN HEMT dc performance, pulsed characteristics and trap densities will be investigated.

AlGaN/GaN HEMT heterostructures were grown on semi-conducting 6H-SiC substrates. The epi-layers consisted of a thin AlN nucleation layer, 2.25 μm of Fe-doped GaN buffer, 15 nm of Al0.28 Ga0.72N, and a 3nm undoped GaN cap. The HEMTs employed dry etched mesa isolation, Ti/Al/Ni/Au Ohmic contacts alloyed at 850 °C, and dual-finger Ni/Au gates patterned by lift-off. The gate length was 1µm, and gate width was 2×150 µm. Both source-to-gate gap and gate-to-drain distances were 2 µm. The drain step-stress condition were set for holding 60 seconds at each drain voltage step, while grounding the source electrodes and maintaining as VG = -8V. The stress started at VDS = +5V, and the voltage step was +1V.  Annealing was conducted for 10 min at 450 °C under a N2 atmosphere using a Steag 100CS rapid thermal annealing system. An automated temperature control chuck from Wentworth was used to perform temperature dependent measurements. The base temperature was varied from room temperature to 300 °C and held constant during the measurement. The device dc characteristics were measured with a HP 4156 parameter analyzer.

It was reported by several groups that gate metal diffusion and notches formed on the AlGaN/GaN layer along the gate edges on both source and drain sides [1,2].  These defects were suggested to be the causes of permanent device degradations for lowering drain current on/off ratio and saturation drain current as well as increasing reverse bias gate leakage current.  However, with a 10 min annealing in nitrogen ambient at 450°C, the degradations of drain current on/off ratio, gate leakage and saturation current recovered, as illustrated in Figure 1.  Thermal annealing process will not reverse the gate metal diffusion nor alleviate notch formation on the AlGaN/GaN layer.  Since the annealing can recuperate the dc performance, the degradations of HEMT dc performance after off-state drain-voltage step-stress are not related to the gate metal diffusion nor the notch formation on the AlGaN/GaN layer.  Post-processing annealing at around 400-450°C has been suggested to enhance device dc performance in terms of lowering gate leakage current and enhancing drain saturation current [3,4].  It was suggested that thermal annealing could remove shallow traps.  Temperature-dependent sub-threshold swing analyses were conducted to extract trap density, as shown in Figure 2.  The trap density increased from 4.66 × 1012 /cm2-V to 1.04 × 1013 /cm2-V after off-state step-stress and recued to 7.3 × 1012 /cm2-V after 450°C annealing.

In conclusion, the new degradation mechanism of dc performance for off-state drain-voltage step stressed AlGaN/GaN HEMT was proposed.  Shallow traps were responsible for the degradation instead of gate metal diffusion or notch formation on AlGaN/GaN layer along the gate edges and the device degradation can be removed with a 450°C annealing. 



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