Influence of Substrate on Hafnium Silicate Metal-Insulator-Metal Capacitors Grown by Atomic Layer Deposition

Metal insulator metal (MIM) capacitors are fundamental components of the electronic circuitry commonly found in many devices in areas such as analogue to digital conversion, micro-electromechanical systems, medical, automotive and memory applications [1-4]. Current MIMCAPS generally employ optimised low dielectric constant (k) materials (k~3.9 - 7) to attain the target electrical properties of high breakdown field and low current leakage. However, device scaling is limited due to the low k value of these materials and this presents a significant challenge to the future development of these technologies [5]. Many high k materials are under investigation to replace these lower k dielectrics to substantially increase the maximum capacitance density and reduce the area associated with the integration of MIM structures.

In this work we investigate the growth of hafnium silicate films by plasma assisted atomic layer deposition on a metal electrode. The hafnium silicate film was deposited using Tetrakis(dimethylamino)hafnium (TDMAHf) and Tetrakis(dimethylamino)silane (TDMASi) precursors at 250^oC with a remote oxygen plasma (300 W).  From HR-TEM analysis and Raman spectroscopy it has been observed that the main crystalline phase is monoclinic HfO₂. This crystallographic phase appears to be templated by the underlying titanium adhesion (10 nm) layer through the platinum electrode (200 nm).

The HR TEM analysis also reveals the presence of nanoparticles, located primarily towards the lower platinum metal layer. Based on electron energy loss spectroscopy (EELS) analysis the nanoparticles are consistent with silicon oxide inclusions, located at HfO₂ grain boundaries.  In addition, the presence of additional phases was detected; these included a super-cell structure within the bulk and an amorphous phase. No hysteresis was observed in the capacitance voltage measurements and the material was observed to exhibit a k value of ~18.

References

[1] C. Zhu et al., IEDM Tech. Dig., 879–882 (2003).

[2] S. J. Kim et al., IEEE Elec. Dev. Lett., 25 (8), 538–540 (2006).

[3] F. El Kamel et al., Appl. Phys. Lett., 91 (17), 172 909 (2007).

[4] A. Hastings, “The Art of Analog Layout”, Prentice Hall, New Jersey, 2001.

[5] C. H. Ng et al., IEEE Elec. Dev. Lett. 24 (8), 506 (2003).