Direct Formation of Monolayer Graphene on SI-Based Dielectrics

Wednesday, 27 May 2015: 17:20
Lake Ontario (Hilton Chicago)
P. Nguyen, V. Berry (University of Illinois at Chicago), and M. Seacrist (SunEdison Semiconductor)
Graphene – a one atom thick planar sheet of carbon atoms – possesses a distinct combination of properties including ultrahigh carrier-mobility, ultrafast photodetection, sensitivity, tunable spintronics, strong/tunable optical absorption, carrier controlled interband/optical-transition, and quantum interference. To incorporate it into the semiconductor industry, direct growth of wafer scale, high-quality, monolayer graphene on silicon-based dielectrics (SiO2 and Si3N4) is desired for the next step towards graphene electronics. In this talk, we show that thin copper (Cu) film on SiO2 or Si3N4 dielectric (electron beam evaporation) can be employed for direct growth of high-quality graphene via chemical vapor deposition (CVD) process. Here, precursor methane (CH4) gas is diffused through Cu grain boundaries to the interface between Cu and selected Si based dielectric, where it is catalytically dissociated into active carbon species at elevated temperature. Further, optimization of the process parameters (temperature, CH4/H2 flow rate ratio, and total pressure) leads to the formation of a uniform continuous, large-area graphene monolayer directly on top of the chosen dielectric. Raman spectroscopy and selectrive area electron diffraction (SAED) are employed for graphene’ structural characterization. The Raman D-peak, G-peak, and 2D-peak occur at characteristic ~1350 cm-1, ~1600 cm-1, ~2700 cm-1 respectively. The ID/IG ratio (~ 0.25 ) corresponds to a graphene cyrstalline sp2 domain size of 17 nm. The I2D/IG ratio (~1.4) confirms the formation of graphene monolayer. Moreover, SAED measurements show single hexagonal pattern, and a d-spacing of 2.44, which also validates the formation of monolayer graphene on chosen dielectric. The electrical properties of the produced graphene will also be presented. Our patented method allows us to achieve high quality wafer sized graphene on silicon based insulating substrate without the need of graphene transfer.