(Invited) Heterogeneous Nano- to Wide-Scale Co-Integration of Beyond-Si and Si CMOS Devices to Enhance Future Electronics

Monday, 25 May 2015: 08:30
Conference Room 4M (Hilton Chicago)
A. Thean, N. Collaert (Imec), I. P. Radu (IMEC), N. Waldron, C. Merckling, L. Witters (imec), R. Loo (imec, Belgium), J. Mitard, R. Rooyackers, A. Vandooren (Imec), A. Verhulst (imec), A. Veloso (Imec), D. Yakimets, T. H. Bao, D. Chiappe, A. Vaysset, O. Zografos (imec), M. Caymax, C. Huyghebaert, K. Barla (IMEC), and A. Steegen (imec)
With the growing need to pack more functionality into a smaller form-factor while providing significant power-performance benefits, future electronics will need fairly disruptive solutions to overcome the mounting limits of Si CMOS scaling. At the core of the hardware innovations will be new process technologies that not allow for more power-efficient CMOS transistors but also specialized devices to enable new on-chip functionality, E.g. Near-Threshold Logic, High-speed I/O, Optoelectronics, etc.

Heterogeneous integration ranging from TSV-based chip stacking to monolithic 3-D integration are active areas of R&D with the common aim to enhanced chip density and functionality. In order to leverage the dense Si CMOS logic and memory fabric, most, if not all approaches also require the integration to be compatible, to different extent, with large-scale 300mm CMOS processes, and potentially >300mm wafers, in the future. At the finest grain, co-integration of different beyond-Si crystalline material (E.g. III-V, Ge, SiGe, etc.) with Si require significant innovations in defect, stress, and process thermal-budget management.

With the maturation of epitaxy process technology, the ability to combine materials of large lattice mismatch is becoming possible with lowering defectivity. Through defect engineering, we will soon have options to integrate IIIV and Ge-based material on Si at different scale, from global wafer level to fine-grain local levels of the order of circuits and devices (Figs. 1 and 2). This opens up possibilities to integrate heterogeneous devices that leverage the unique properties offered by epitaxial combination of materials.

Besides high-channel carrier mobility, integrating compound semiconductors heterostructures into multi-gated nano-devices like FinFETs (Fig. 3) combines Fin structural confinement with quantum well confinement enhancing the electrostatics of FinFET structures (Fig. 4). Due to the intrinsic lower band-gap of high-mobility channels (InGaAs, Ge, etc.), which leads to increase band-to-band tunneling leakage, there may be a need to co-integrate wider band-gap devices to address the low-leakage components (Eg. Low-standby leakage circuits, High-density SRAM, etc.) at the system level. Hence, a method of integrating different channel materials on the same die is called for.

With the flexibility to direct heteroepitaxy on Si, the possibility to build hybrid systems of novel devices and MOSFETs become real. For example for an ultra-low Vdd Tunnel-FET (for ultra-low Vdd logic) process may be achieved by a grow-and-etch approach or by an epitaxy replacement process on Si. For example, with source replacement, asymmetric vertical device structures can be integrated in the form of TFETs (Fig. 7). Polarity and performance of TFETs can be selectively modulated by the source material replacement process (Fig. 8). The mix and match of different devices and circuits will need careful considerations of circuit layouts, which bring new parasitic factors (Fig. 9) which will need to be overcome. Extending beyond integration of 3-D semiconductors, further heterogeneity with emerging materials like 2-D Transition metal dichalcogenides crystals and spintronics offer even richer possibilities for future on-a-chip electronic systems. This paper will look into the materials, process, device and circuit considerations to enable monolithically-integrated heterogeneous materials, devices, and systems.