Increasing the Energy Storage Capability of Porous Silicon Electrochemical Capacitor Devices

Integrated on-chip energy storage is increasingly important in the fields of internet of things (IoT), energy harvesting, and sensing. Silicon is already the materials of choice for the integrated circuits found in every IoT device and there are numerous research efforts to integrate energy harvesting devices on-chip, however the effort to integrate electrochemical (EC) capacitors on a silicon die has been limited. Unlike batteries, EC capacitors are electrostatic devices and do not rely on chemical reactions enabling cycle lifetimes of >1M. This is especially important for off-power-grid IoT devices where difficulty associated with regularly replacing the batteries of billions of devices is prohibited. The electrochemical limits for the porous silicon based devices are measured and then techniques for increasing the energy and power capacity are explored.

EC capacitors were prepared using porous silicon nanostructures and silicon process methods. Devices were fabricated with tapered channels sized from 100 nm at the top to 20 nm and with aspect ratios greater than 100:1. Surface coatings were necessary for long-term stability because unpassivated silicon structures react with the electrolyte. To obtain uniform coatings using stop-flow atomic layer deposition (ALD), efficient surface reactions are needed between high volatility, low molecular weight, small molecular diameter precursors without chemical vapor deposition side reactions. TiCl₄ and NH₃ precursors were found to coat porous Si with TiN uniformly. Measurements of coated P-Si capacitors reveal that an areal capacitance of up to 6 mF/cm² can be achieved using 2 μm deep pores, and scales linearly with depth with 28 mF/cm² measured for 12 μm deep pores. Three-terminal CV measurements with EMI-BF₄ ionic electrolyte were used to examine the stability of different pore sizes and TiN coating thicknesses. TiN fabricated using 300 ALD cycles were stable whereas those prepared using 200 cycles were not (see Fig. 1). Furthermore, pores with an average 50 nm width and 100:1 aspect ratio were stable to ±1.2 V when cycled at 10 mV/s and stable to ±1.0 V when cycled at 1 mV/s. Smaller 30 nm wide pores (166:1 aspect ratio) showed some degradation at the cathode when cycled at 1 mV/s at ±1.0 V. The electrochemical window is limited by the cathode to approximately 2.4 V for a symmetrical device, but could be increased using asymmetric electrodes. Different ionic liquids were studied to determine the ionic liquid best suited to TiN coated porous Si including TEA-BF₄/acetonitrile (AN), EMI-BF₄, EMI-Tf, and a 3M EMI-BF₄/propylene carbonate (PC) mixture. The relative increase in capacitance density obtained from using TEA-BF₄/AN, 3M EMI-BF₄/PC, EMI-BF₄, or EMI-Tf was 1:2.7:2.7:3.5 relative to TEA-BF₄/AN respectively with EMI-Tf giving the best results. Using impedance spectroscopy, the time constant for a 2 μm deep porous Si EC capacitor with a high conductivity TiN coating was found to be 17.6 ms which is fast enough that this can be used for applications involving AC filtering for AC-DC conversion. The volumetric energy density versus power density of porous Si devices versus other devices plotted in Fig. 3 show several orders of magnitude more energy density than electrolytic capacitors with a similar voltage range. Also, these results are between one to two orders of magnitude higher than the other studies utilizing porous silicon. Finally, to increase the total stored energy and operating voltage, samples were prepared with silicon that had pores etched into both sides of the substrate using a double cell HF tank system with electrolytical backside contact. The substrates were then stacked resulting in electrochemical capacitors in series thereby doubling the maximum voltage to 5 V and also doubling the total energy stored.