1168
(Invited) Interface and Dielectric Engineering for High-Performance Top-Gated MoS2 Field Effect Transistors
Here, we explore the case of interface engineering by utilizing an ultrathin metallic oxide (MgO, Al2O3 and Y2O3) buffer layer inserted between the ALD-HfO2 and MoS2 channel in order to achieve conformal HfO2/MoS2 interfaces with the minimal interface defect density. Exploiting these enhanced gate stack dielectrics, we attain the highest saturation current (526 μA/μm) of any MoS2 transistor reported to date, which is comparable to the same scaled state-of-the-art Si MOSFETs. At the same time, these devices also exhibit the impressive room-temperature mobility (63.7 cm2/V·s), on/off current ratio (>108) and near-ideal sub-threshold slope (SS = 65 mV/decade).
Although Y2O3/HfO2/MoS2 structure improves the device performance greatly, the degradation in mobility is unavoidable. We then further utilize BN as dielectric layer to improve the mobility of top-gated MoS2 device. The mobility value is close to 100 cm2/V·s,
Demonstration of all these suggests that the performance of few-layer MoS2 FETs can reach near intrinsic limits at room temperature along with the proper interface engineering and propose future directions to improve electrical characteristics in layered semiconductors.