Low resistivity junctions and contacts are essential for fabricating high performance devices with advanced device nodes. Significant effort has been expended towards the development of low resistivity junctions. However, low resistivity contact formation has not received significant attention. The silicide of choice has been changed from high temperature silicide to low temperature silicide (i.e., WSi → TiSi₂ → CoSi₂ → NiSi) depending on the allowed maximum process temperature and required minimum line width for the device node. Once the candidate silicide material is chosen for the device node, relatively small improvements in resistivity and small changes in the silicide formation process have been made in recent years, despite silicidation process optimization. This includes fine tuning of silicide formation conditions for types of Si (i.e., doped poly Si, NMOS and PMOS), modifications of process steps and integration schemes.

In this study, we have investigated the effect of substrate type on CoSi₂ formation in rapid thermal annealing (RTA). The RTA temperature and time sensitivity of the resulting resistivity of the Co₂Si contacts with P-doped poly-Si, NMOS source/drain (S/D) and PMOS S/D were investigated for process window determination using a single wafer furnace (hot wall)-based RTA system.

The type of Si had a significant effect on the resulting CoSi₂ formation temperature and contact resistance was observed. With the increase of RTA time, the CoSi₂ formation temperature was reduced and the difference of CoSi₂ formation temperature for different Si substrates became larger. Depending on CoSi₂ integration schemes (i.e., one step (for all CoSi₂ in poly-Si gate and S/D) or two step (one for CoSi₂ for poly-Si gate and the other for CoSi₂ for S/D)), the CoSi₂ formation RTA conditions must be modified. Detailed effects of substrate type on CoSi₂ formation and process windows will be reported.