In the ultra-large-scale integration (ULSI) technologies, polysilicon resistors are usually employed in the integrated circuits as a precise analog resistor element for a variety of applications, such as DAC (digital resistor give the solution of the linearity and Rs concerns to analog converter) in analogue circuits [1-3]. Conventionally the polysilicon resistance can be adjusted by ion implantation and post annealing process [4]. For the self-aligned implantation process, the dosage changes which are always utilized to adjust the resistance are feasible to induce the MOS characteristics changes, especially in the submicron process whose short-channel effects (SCE) are much more sensitive to the dosages [5]. In this work, we propose a new inner anneal process in N₂ambient after polysilicon re-oxidation to reduce the polysilicon resistance by changing the polysilicon grain size.

    The test patterns are manufactured on 300mm-diameter wafer by 65-nm 1-poly 7-metal standard CMOS technology. After polysilicon re-oxidation to form oxide film on polysilicon surface, the wafers are annealed at 800^oC, 900^oC, 950^oC and 1000^oC in N₂ambient, respectively. Fig. 1 shows the process flow and annealing process steps in the flow. After anneal, the polysilicon grain size is measured by X-ray powder diffraction (XRD). And the electric characteristics for NMOS, PMOS and polysilicon resistance are tested.

    Fig. 2 shows the poly resistance reduction proportion and poly grain size after anneal at 800^oC, 900^oC, and 1000^oC for 5min, and 950^oC for 20min in N₂ ambient, respectively. Only after annealing at 950^oC or above for 5min, the resistance can be obviously reduced, due to the poly grain size increasing. Fig. 3 shows threshold voltages (Vt) variation proportions of NMOS and PMOS owning gate length of 65nm and width 0.12µm after utilizing annealing process at different temperatures. PMOS is more sensitive to the anneal process than NMOS. But after anneal at 950^oC or below, the threshold variation for both NMOS and PMOS is less than 5%, which is acceptable for the integration process manufacturing.

    A new anneal process at N₂ ambient to adjust the polysilicon resistance has been proposed. It has been verified that utilizing anneal process at 950^oC or below, the 65nm MOS performances can be maintained almost same as before. Consequently, it is considered that the anneal method can be to be applied to the deep submicron integration process.

References

[1] C. D. Parikh, and R. M. Patrikar, Solid-state Electronics, 43, 683 (1999).

[2] R. Murii, and M. J. Deen,, IEEE Trans. Electron Devices, 49, 187 (2002).

[3] C. Uang, H. Chuang, S. Tsai, K. Thei, P. Lai, S. Fu, Y. Tsai, W. Liu, IWJT, 293 (2004).

[4] S. Gupta, J. Electrochem. Soc. 149, G271 (2002).

[5] R. H. Dennard, F. J. Gasensslen, H. M. Yu, V. L. Rideout, E. Bassous, A. R. Leblanc,  Solid-state Circuits Soc Mag. IEEE, 87, 668 (1999).