1182
(Invited) Graphene Plane Electrode for Low Power 3D Resistive Random Access Memory

Tuesday, 31 May 2016: 14:00
Indigo 206 (Hilton San Diego Bayfront)
S. Lee (Stanford University, Kyunghee University), J. Sohn, Z. Jiang, H. Y. Chen, and H. S. P. Wong (Stanford University)
The central theme of the “Internet of Things” is a societal and technological movement towards ubiquitous, abundant-data computing. Such transformation requires real-time analytics on enormous quantities of data collected by a vast network of sensors and other autonomous sources feeding into the data cloud. Current computing technology, however, cannot satisfy such applications with the required throughput and necessary energy efficiency. The next technology frontier will be monolithically integrated chips with 3-dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene plane to assemble a resistive memory stacked in a vertical 3D structure. Compared to the same architecture that uses conventional metal (Pt) as an RRAM electrode, the atomically thin graphene edge electrode was able to reduce power consumption by ×300 while producing a highly localized electrical field for oxygen anion migration. The switching energy of this device is one of the lowest reported compared to existing alternative memory technologies. Importantly, circuit analysis of the 3D architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices