Resistive Random Access Memory (ReRAM) devices are considered promising candidates for emerging Non-Volatile Memory (NVM) applications. ReRAM devices can be switched at very low voltages using ultra-fast pulses. In addition, these devices can be easily integrated in Complementary Metal Oxide Semiconductor (CMOS) process-flow due to simplistic configuration, materials and process compatibility. These properties make them attractive for not only stand-alone off-chip memory applications but also for low-power embedded memory applications. However, there are several challenges that need to be addressed to take the complete benefit of this enabling technology. For example, currently available ReRAM devices suffer from variability and limited endurance. Additionally, these devices need a careful control of current, referred to as compliance current (CC), during electroforming and set operations which is typically achieved using a current limiting circuitry or an on-chip transistor. A tight control of CC is needed to control the filament dimension during forming and set operations of ReRAM to prevent the permanent breakdown of the device. However, the necessity of current limiting circuitry or transistor makes the integration of ReRAM devices in crossbar architectures difficult in 1Diode-1ReRAM (1D1R) configuration using bidirectional diodes as selector devices. Therefore, there is an urgent need to develop ReRAM devices which are self-compliance current (SCC) controlled where no additional current limiting circuitry or transistor is needed to limit the current through the device. This paper will discuss the role of interfacial layer (IL) engineering between electrodes and switching oxides towards achieving SCC ReRAM devices. Experimental results will be presented to show routes to scale down the switching currents in SCC ReRAM devices via the control of compositions and thicknesses of IL. Device performance parameters including endurance, retention, and reliability characteristics of these devices will be discussed. Finally, mechanism behind SCC and device models will be discussed which can be used for circuit level simulations.