Power semiconductor devices have attracted increasing attention as key components in a variety of power conversion systems. Although the performance of Si power devices has remarkably been improved, silicon carbide (SiC) (and gallium nitride (GaN)) is promising for advanced low-loss and fast power devices, which can substantially outperform Si-based power devices [1-3]. Because of its strong bonding energy and thermal stability, however, special cares must be paid for fabrication process of SiC devices. This paper reviews present status and challenges of device processing technologies in SiC. In particular, ion implantation and MOS technologies are highlighted, because of their uniqueness, importance, and difficulty.

Ion implantation is a key process in fabrication of almost all kinds of SiC devices, due to the extremely small diffusion constants of dopants in SiC. Wide-range doping control of both n- and p-type conductivity can be achieved by ion implantation, but post-implantation annealing at unusually high temperature over 1650 ^oC is required to achieve nearly perfect electrical activation. Such high-temperature annealing may cause incongruent evaporation of silicon and surface roughening. The surface roughening can be significantly minimized by using a carbon cap. If the as-implanted lattice damage is of near-amorphous level, lattice recovery is very difficult. Therefore, implantation at elevated temperature is often employed, especially when the implant dose is very high. A variety of extended and point defects are generated by ion implantation in SiC and many of these defects survive after the post-implantation annealing. Thus, designing of device structure (implanted regions) and the process control are critical for fabrication of high-performance SiC devices.

SiC power MOSFETs are an ideal power switch owing to the low on-resistance and fast switching. However, the interface properties of SiO₂/SiC MOS structures are still far from a satisfactory level, severely affecting the performance and reliability of SiC power MOSFETs. As in the case of Si power MOSFETs, high dielectric property of the gate oxide, high channel mobility, high threshold voltage and its stability are required. Though recent study on MOS structures formed on nonpolar SiC faces (a- and m-faces) has exhibited some promise (reasonably high mobility of 100 cm²/Vs and threshold-voltage stability), basic understanding of SiC MOS physics is still missing. To overcome the limitations of interface characterization techniques, a new method has been developed to accurately characterize the interface states near the band edge, and a clear correlation with channel mobility has been found. Based on these results, several trials to further improve the SiC MOS interface are under investigation.

[1] J.A. Cooper, Jr. and A. Agarwal, Proc. IEEE 90, 956 (2002).
[2] T. Kimoto, Jpn. J. Appl. Phys. 54, 040103 (2015).
[3] T. Kimoto and J.A. Cooper, Fundamentals of Silicon Carbide Technology (John Wiley & Sons, 2014).