GaN devices are promising candidates for the next generation power devices for energy efficient applications. Although astounding performance is already proven by many research papers, the widespread adoption of GaN power devices in the market is still hampered by (1) yield and reproducibility ; (2) cost ; (3) reliability. All three factors are to be considered, but to convince customers to adopt GaN power devices in their next generation products, proven device and product reliability is a must.  Cost is kept acceptably low by growing the GaN epi stack on 6inch and 8inch Si substrates, and by processing the GaN power device technology in standard CMOS production lines, with a proper contamination control protocol in place.

This paper will focus on the most important intrinsic reliability mechanisms for GaN power devices. It will cover gate dielectric reliability, Ohmic contact reliability, accelerated drain stress testing (high temperature reverse bias--HTRB) and high voltage device wear-out testing (high voltage off-state stress--HVOS). The need to do reliability investigations based on statistical data on large area power transistors (100+ mm gate width) instead of small test structures will be emphasized. Acceleration models and statistical distribution models (Weibull, lognormal) are discussed.  The correlation between the GaN buffer stack vertical leakage and the parametric drift in prime device parameters under accelerated stress will be highlighted.

Furthermore, since the MOCVD epi layers of the GaN-on-Si buffer stack are key to the device performance, a measurement strategy to extract valuable information about the physical properties of the buffer layers (e.g. activation energies of the traps, conduction mechanisms, …) based on simple transmission line structures, is outlined.  This information will also be linked to the so-called “dynamic Ron”, a recoverable reduction in on-state current due to the trapping of charges in the buffer stack and/or the interface.

Finally, it will be shown that through proper engineering of the epi buffer stack, device layout and device passivation scheme, dynamic Ron-free power transistors can be obtained.