Shallow trench isolation (STI) divot profile usually affects MOS transistor electrical properties, such as drain current (Id) versus gate voltage (Vg) double hump curve (kink effect), due to parasitic transistor formation. Slightly STI divot is acceptable in most logic processes. However, it is observed that under the same STI SiO₂ etching amount, gas phase chemical etching divot level is around 55% reduced by comparing with conventional batch type wet chemical (dilute HF) etching, showed in Figure 1.

Divot levels difference between gas phase etching method and conventional wet etching method was observed. In this study, some key points had been defined, showed as Figure 2, to monitor STI SiO₂ loss phenomenon during different etching methods. Point a is STI vertical top SiO₂ loss amount; point b is STI sidewall top SiO₂ loss; point c is STI sidewall bottom SiO₂ loss; b/a is the SiO₂ loss ratio of STI sidewall top to vertical top; c/a is the SiO₂ loss ratio of STI sidewall bottom to vertical top.

To figure out the behavior of STI SiO₂ loss, single wafer spin wet etching method was added and split three spin speed conditions as 800rpm, 1500rpm and 2200rpm. Figure 3. showed TEM images of STI etching by gas phase, batch type DHF and spin type DHF process. Table 1 and Figure 4 showed a, b, c values of above etching methods.

Normally, isotropic etching rate will be affected by geometry effect. Larger etched surface exposed results in higher etching rate due to different surrounding reactant amount, showed as Figure 5. That means the ratio (c/a) of STI vertical top SiO₂ loss to sidewall bottom SiO₂ loss should be less than 1 theoretically, which had been observed in batch DHF etching method.

However, from Figure 4, spin type DHF etching method showed c/a ratio larger than 1. Based on Bernoulli's effect, reactant (HF₂^-) at STI top will be dragged down to the STI sidewall bottom area due to higher DHF flow speed in small tunnel area. Higher flow speed induced thinner boundary layer, and sufficient reactant makes STI sidewall bottom etching rate increasing. The mechanism showed as Figure 6.

By increasing spin speed from 800rpm to 2200rpm, c/a ratio changed from 1.13 to 1.03, approaching to batch type value 0.91. Higher spin speed also increased DHF flow speed at STI top and minimized the flow speed difference between STI top and sidewall bottom.

For gas phase chemical etching, HF and NH₃ mixing gas is usually used for SiO₂ etching, and byproduct (NH₄)₂SiF₆ is generated and deposit on SiO₂ surface which will interfere following reactants diffusing toward SiO₂ surface for further etching reaction. As byproduct thickness increasing, finally, etching stop due to no reactants touching fresh SiO₂ surface. The mechanism showed in Figure 7. c/a ratio less than 1 can also be found in gas phase etching method, and much less than 1 due to the combination effect of geometry and byproduct interfering.

Table 2 showed each etching method characteristics and merit/ demerit, gas phase etching has no water mark issue and has well divot control capability. Both batch type and spin type DHF etching methods have water mark risk, but spin type DHF etching method can prevent wafer surface particle redeposit.

Spin type wet etching process becomes mainstream in semiconductor foundry due to excellent particle defect performance, but higher chemical flow speed inducing higher etching rate in STI SiO₂ small tunnel and causing deeper divot, although increasing spin speed can minimized the divot level. Gas phase type etching has intrinsic diffusion barrier of etching byproduct. Combining gas phase and DHF etching methods for all STI SiO₂ etching processes can get expected final divot profile or only using gas phase etching method can achieve excellent divot control capability in logic 28nm generation or more advanced MOSFET fabrication processes.