Background/ Objectives and Goal
Silicide techniques are widely used for high-performance logic devices as the device dimensions become small towards sub-100 nm due to the source / drain sheet resistance issue.NiSiprocess has several advantages.They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance,and(6) smaller contact resistance for both n- and p-Si[1].We, therefore, propose a nickel silicide junctionlessFinFETdevices.
2. Methods
Fig.1. depicts schematically view of the high-K metal-gate nanowire junctionlessFinFETwere fabricated on a 6-inch wafer with a 40 nm-thick silicon dioxide layer.The active layer with ten strips of NWs was defined by electron beam (e-beam) and transferred by reactive ion etching.An 33 nm dry SiO2 layer was grown on the active layer. Next,implanted (boron for pFETs and phosphorus for nFETs,dosage of 2 × 1014 cm2) and followed by thermal anneal in the channel.The samples were then dipped in HF solution for NWs. 3 nm of HfO2was deposited by ALD on the nanowires as gate dielectric, followed by the PVD 50 nm TiN for gate metal.After the deposition,electron beam (e-beam) defined gate contact and transferred by reactive ion etching.Next, 15 nm of titanium followed by 15 nm of nickel was deposited on the sample.NickelSilicide was formed after twice microwave anneal.First annealed by microwave with 360W for 300 sec , and1300W for 300sec. The temperature profiles versus annealing time are shown in Fig. 2[2].
3. ExpectedResults/Conclusion/Contribution
The ID–VGcharacteristics of a 15 nm gate-length high-k metal-gate nanowire junctionlessFinFET Fig. 3.The on-current value is comparableto that of a junctionlessfinfetwith the same bias conditions.In our experiment,there was no metallization past the silicide layer, therefore the resistance of the devices was large.This is the reasons why devices without silicide showed less on-current presented here.
We have demonstrated high-k metal-gate nanowire junctionlessFinFET with nickel silicide fabricated with a low-temperature process.The devices have exhibited a competitive short-channel behavior and a much-improved drive current.These results indicate that silicide S/D is a promising option for a nanowire junctionlessFinFET device.We believe that this letter significantly advances the state of the art for low-temperature silicide junctionlessFinFET.
REFERENCES
[1] H. Iwai, T. Ohguro, and S. Ohmi, “NiSi salicide technology for scaled CMOS,” Microelectron. Eng., vol. 60, no. 1/2, pp. 157–169, Jan. 2002
[2] Y.-J. Lee et al., “Low-temperature microwave annealing processes for future IC fabrication—A review,” IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 651–665, Mar. 2014.