Trends in the electronic industry require smaller and smaller components resulting in transistor sizes down to the nano-scale. This is starting to pose significant manufacturing problems. In classical scaled transistors one has to form two junctions, since source and drain regions are separated by channel area with opposite doping polarity. The diffusion of source and drain doping atoms is difficult to control in very short-channel transistors as shown in Figure 1. In all transistors, the diffusion of source and drain impurities into the channel region becomes a bottleneck to the fabrication of very short-channel devices, and very low thermal budget processing techniques must be used [1].

An electrical junction refers to a thermoelectricity junction, a metal-semiconductor junction or a p-n junction (p-type semiconductor to n-type semiconductor junction). Typically, Metal Oxide Semiconductor (MOS) transistors are made using two p-n junctions: the source junction and the drain junction. An n-channel transistor is an N-P-N structure. A p-channel transistor is a P-N-P structure.

Very costly techniques are used to minimize this diffusion, but even in the absence of diffusion the statistical variation of the impurity concentration due to ion implantation or other doping techniques can cause device parameter variation problems. There arises therefore, the need to provide a transistor device structure that overcomes the above-mentioned problems.

Ideally, it should be possible to completely deplete the semiconductor film of carriers, in which case the resistance of the device becomes quasi-infinite. In a multigate FET (MugFET) the gate electrode is wrapped around a silicon wire, called “finger” or “fin”, forming a wrapping gate structure with excellent control of the channel electrostatics. The excellent gate-to channel coupling allows one to fully deplete the channel region even if it is heavily doped.

The junctionless transistor (JNT) is fabricated without source and drain formation process, as the doping type and concentration in the channel region is essentially equal to that in the source and drain, or at least to that in the source and drain extensions [2-9]. These devices are essentially junction-free as shown in Figure 1. JNT is basically a fully depleted accumulation-mode device, consisting of a heavily-doped SOI nanowire resistor with a MOS gate to control current flow.

Doping concentration is constant and uniform throughout the device and typically ranges from 10¹⁸ and 10²⁰ cm^-3. The JNT device can be tuned to normal-off state when the gate work function is properly chosen and the highly doped channel can be fully depleted with no gate bias. As gate voltage is increased, the JNT enters into partially depletion state, and current conducts in the center of the nanowire when V_D is supplied, and then at flatband voltage, the depletion region is completely gone. The accumulation starts at the nanowire surface when further raises the V_D, which additionally offers an accumulation current, in spite of the bulk current.

This talk will first focus on the revolution of the junctionless transistor, focusing on the initial reports and studies in 2010.

Then the evolution of the junctionless transistor will be discussed since the early reports in 2010. The variety of studies will be reviewed, as junctionless transistors are being reported in many more materials other than Si, such as Ge and InGaAs [10-11], and very recently in MoS₂ [12] and in other transition-metal-dichalcogenide semiconductors.

References :

[1} Jain SH, et al. Low resistance, low-leakage ultrashallow p+ junction formation using millisecond flash anneals. Electron Devices, IEEE Transactions on. 2005;52:1610-5.

[2] Colinge J-P, et al. Nanowire transistors without junctions. Nat Nanotechnol. 2010;5:225-9.

[3] Kranti A, et al. Junctionless nanowire transistor (JNT): Properties and design guidelines.  Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European: IEEE; 2010. p. 357-60.

[4] Lee C-W, et al., Junctionless multigate field-effect transistor. Appl Phys Lett. 2009;94:053511--2.

[5] Lee C-W, et al. Performance estimation of junctionless multigate transistors. Solid State Electron. 2010;54:97-103.

[8] Colinge J-P, et al. Reduced electric field in junctionless transistors. Appl Phys Lett. 2010;96:073510--3.

[9] Colinge J, et al. Junctionless nanowire transistor (JNT): Properties and design guidelines. Solid State Electron. 2011;65:33-7.

[10] Yu, R., et al., “Impact ionization induced dynamic floating body effect in junctionless transistors”, (2013) Solid State Electronics, 90, pp. 28-33.

[11] Yu, R., et al.. “Device design and estimated performance for p-type junctionless transistors on bulk germanium substrates” (2012) IEEE Transactions on Electron Devices, 59 (9), art. no. 6226451, pp. 2308-2313

[12] Das, S., et al.., “Nb-doped single crystalline MoS2 field effect transistor”, Appl. Phys. Lett. 106, 173506 (2015).