As silicon-based complementary metal-oxide-semiconductor (CMOS) technology obviously approaches its physical limits, a need for its replacement with other materials such as GaAs and InGaAs for high mobility and scalable logic devices has emerged. However, large source/drain (S/D) spacing induced by annealing process to make ohmic contacts obstructed the scaling of III-V devices. Also, Fermi level pinning at metal/semiconductor interfaces caused by metal-induced gap states (MIGS) leads to high contact resistivity. Recently, to prevent the MIGS penetration into the semiconductor, the metal-interlayer-semiconductor (MIS) structure has been studied [1]. In addition, the heavily doped interlayer can reduce specific contact resistivity (ρ_c) more than undoped one, which has been experimentally demonstrated [2, 3]. Because it induce the effect of Schottky barrier lowering and the reduction of tunneling resistance. Although GaAs, a representative material of III-V semiconductors, is used in this study to confirm the effect of surface passivation and the MIS structure, other III-V semiconductors such as InGaAs and InAlAs can be applied to this proposed method.

The surface of n-GaAs substrates, passivated by using the SF₆ plasma, were prepared. Because the SF₆ plasma treatment has the effect of S and F passivation simultaneously, the SF₆ plasma treated samples exhibit better electrical performance than (NH₄)₂S solution passivated samples as shown in the Fig. 1. Figure 1 shows the I-V characteristics and the ρ_c of the SF₆-treated MIS contacts using a ZnO and an Aluminum-doped ZnO (AZO) as interlayers. The ZnO based interlayers have an advantage of low tunneling resistance due to its low conduction barrier offset (CBO) to GaAs, compared to other dielectric materials such as Al₂O₃, and SiN [4]. Also, the heavily doped ZnO, such as AZO, leads to more improve the electrical properties than those of undoped one because the thin ZnO depletion region, caused by aluminum doping, induces reduction of the tunneling resistance. In the Fig. 1(a), both current densities of the SF₆-treated MIS contacts are higher than non-passivated, (NH₄)₂S-passivated, and SF₆-treated metal-semiconductor (MS) contacts. And the AZO inserted MIS contact has more improvement of current densities than the ZnO inserted MIS contact. The ρ_c ratio of the SF₆-treated MIS contacts to the non-passivated MS contact are shown in the Fig. 1(b) and the Ti/AZO (2 nm)/SF₆-treated n-GaAs (~2 × 10¹⁸ cm^-3) contact exhibits the minimum ρ_c which presents ~10⁵ × reduction from the Ti/non-passivated n-GaAs contact. And also it exhibits 10 times lower than that of our previous work, the Ge-passivated MIS contact [5].

In this study, we have experimentally demonstrated the Fermi-level unpinning through the MIS structure by inserting an AZO interlayer. A ~10⁵ × reduction in ρ_c is achieved in the Ti/AZO (2 nm)/SF₆-treated n-GaAs contact compared to Ti/non-passivated n-GaAs. Therefore, this proposed MIS structure can be used as non-alloyed S/D ohmic contacts in beyond CMOS technology.

[1] A. Agrawal et al., APL, 101, 042108 (2012).

[2] G.-S. Kim et al., IEEE EDL, 35, 1076-1078 (2014).

[3] S. Gupta et al., JAP, 113, 234505 (2013).

[4] J. Hu et al., JAP, 107, 063712 (2010).

[5] S.-H. Kim et al., IEEE EDL, 36, 884-886 (2015).