GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) have demonstrated outstanding high-power and high-frequency performance [1]. However, the large amount of surface states at the GaN surface, which cannot be totally removed, leads to the current slump when the GaN HEMTs operate under the high drain bias [2]. Therefore, the surface passivation becomes a very important issue for GaN HEMT power device. To eliminate the surface states at the GaN surface, many groups have performed different passivation methods using different deposition techniques, materials, and surface treatments. However, only a few papers reported the correlation between device performance and the surface potential due to the passivation with different charge density. The effect of charge passivation was demonstrated in this study. It was reported that SiON has high density of positive fixed charge (Q_f) in the bulk due to the incorporation of nitrogen into oxide which generates high density of positively charged K⁺center [3]. The positive fixed charges at the SiON/GaN interface can reduce the negative GaN surface potential, expanding the 2DEG quantum well below the Fermi level and stabilizing the 2DEG carrier density when the device operates under high electric field. Thus, SiON has many desired properties as the passivation layer and gate insulator for GaN MIS-HEMT.

The AlGaN/GaN HEMT heterostructure was grown by metal-organic chemical vapor deposition (MOCVD) on silicon substrate. The 12-nm SiON and SiN films were adopted as the passivation and gate insulator layers for device performance comparison. These films were prepared by plasma-enhanced chemical vapor deposition system at 300°C. The device fabrication features Ti/Al/Ni/Au ohmic contact metal and Ni/Au gate metal. The schematic cross section of the AlGaN/GaN HEMT with passivation layer and gate insulator is shown in Fig. 1. The gate-to-drain spacing L_GD, gate-to-source spacing L_GS, and gate length L_G were 10-μm, 3-μm, and 2-μm, respectively.

The large negative ΔV_th observed for the sample with SiON passivation indicates the existence of high density of positive fixed charge at SiON/AlGaN interface. The density of positive fixed charges were ~2.7 × 10¹³ and ~1.5 × 10¹³ e/cm^-2 for SiON and SiN, respectively. The basic DC I‒V characteristics are shown in Fig. 2. For the sample with SiON passivation, a higher I_DS,max of >1 A/mm, and a lower subthreshold slope (SS) of 68 mV/dec were obtained. In contrast, the sample with SiN passivation exhibits a I_DS,max of ~896 mA/mm, and a SSof 73 mV/dec. It indicates that the positive fixed charges at the SiON/AlGaN interface reduce the negative GaN surface potential and expand the quantum well below the Fermi level, resulting in the increase of the 2DEG carrier density.

The dynamic ON-resistance has been commonly used to examine the trapping effects attributed to the surface and interface states in the GaN device structure [4]. As shown in Fig. 3, the dynamic ON-resistance were extracted by varying OFF-state drain quiescent voltage (V_DSQ) of 0 ~ 100 V and ON-state with V_GS = 0 V, V_DS = 1 V. The ON-state pulse width was 500 μs with a duty cycle of 10%. For the V_DSQstress at 100 V, the dynamic ON-resistance increases slightly to 1.03 times for the sample with SiON passivation. In contrast, the dynamic ON-resistance increases 1.17 times for the sample with SiN passivation. The results reveal that SiON passivation with high density of positive fixed charge for GaN MIS-HEMT is preferable for power device applications.

With high-density positive charge passivation using SiON, the GaN MIS-HEMT demonstrates the improvements in I‒Vcharacteristics and dynamic ON-resistance. Overall, the results demonstrate that the high density of positive charge in the film is a promising passivation and gate insulator for GaN power devices.

Fig. 1. Schematic cross section of the GaN MIS-HEMT

Fig. 2. (a) I_DS–V_DScharacteristics and (b) transfer characteristics for GaN MIS-HEMTs with different passivation and gate insulator layers.

Fig. 3. Switching performance extracted from various OFF-state quiescent bias of 0 ~ 100 V.

[1]       W. Saito, Y. Takada, M. Kuraguchi, K. Tsuda, I. Omura, T. Ogura and H. Ohashi, Electron Devices, IEEE Transactions on 50 (12), 2528-2531 (2003).

[2]       R. Vetury, N. Q. Zhang, S. Keller and U. K. Mishra, Electron Devices, IEEE Transactions on 48 (3), 560-566 (2001).

[3]       Z. Zhuo, Y. Sannomiya, Y. Kanetani, T. Yamada, H. Ohmi, H. Kakiuchi and K. Yasutake, Nanoscale research letters 8 (1), 1-6 (2013).

[4]       D. Jin and J. del Alamo, Electron Devices, IEEE Transactions on 60 (10), 3190-3196 (2013).