The starting substrates are heavily-doped N+ Si wafers, and titanium nitride of 200 nm thickness was deposited on N+ Si substrate as bottom electrode. Then, 5 nm of graphite and 7 nm of HfOx were deposited as RS dielectric layers for bilayer (HfOx/C) structures by RF sputtering method. Pt (165nm) was deposited as top electrodes for RRAM devices (not showed here). Fig. 1 shows bipolar I-V characteristics during DC voltage sweeps for single-layer HfOx and HfOx/C stacked devices. Both SET and RESET voltages are around 1 V/-1 V in single-layer HfOx devices as the bilayer devices possibly owing to inserting a HfOx stack layer, which has higher oxygen concentration and potentially be beneficial for low voltage operating applications. Comparing the bilayer structure to the single-layer HfOx structure, where dI/dV increases indicating that there was significantly increased resistance at low voltage region for sneak path current suppression. The graphite-stacked memristor has been confirmed with the nonlinearity than HfOx single layer structure and was proposed as a solution for sneak path issue in crossbar array applications. Nonlinearity (NL) is defined as the ratio of the current at full read voltage (i.e. -0.6 V) to the current at 1/3 read voltage (-0.2 V). The higher nonlinearity, the better ability is to avoid the sneak current interference. Fig. 2 shows the NL for graphite-stacked RRAM with varied graphite thickness i.e. 0, 3, 5, 8, 10 nm (30 DC cycles). The NL is increasing with the portions of graphite thickness in the bilayer stacks. The single layer and bilayer devices with narrow SET/RESET voltage variation and have been found to exhibit low operating voltage (~1 V), which are independent on the graphite thickness in the bilayer structures (Fig. 3). Fig.4 shows the HRS and LRS of all graphite memristors as compared to HfOx layer device. The memory window i.e. ratio of ILRS /IHRS enlarges in the graphite memristors, which is suggested to the graphite oxide (GO) formation caused HRS current reduction.
The NL characteristics in ILRS of all the devices under different SET compliance current limits (CCL) as showed in Fig. 5. With a thin graphite layer (5 nm) on the bottom of HfOx (7 nm) layer, the NL is ~3x of the single-layer HfOx layer devices. This makes graphite-stacked bilayer devices a potential candidate for 1R selectorless RRAMs. The NL of graphite-stacked RRAM can be optimized by adjusting SET CCL, as called “gap design method” for memristors. To eliminate device-to-device (D2D) variation in RRAM, three graphite-stacked memristors in distanced region have been demonstrated with the gap migration with increasing the SET CCL. Also, the RESET current is critical for overall switching power in RRAM applications, is ~1 mA and has been found to be independent of the thickness ratio of stacks (not showed here). Fig. 6 as the schematic of single layer and graphite-stacked structures shows the graphite memristor is the candidate of selectorless RRRAM since the formation of GO as the low-k material in gap modulation. The graphite layer has been confirmed by the XRD pattern in graphite (400) phase direction with resistivity of 0.2643kΩ as the switching layer in stacks, not as the electrode.
In this study, build-in NL characteristics have been realized for the graphite selectorless memristors without an diode/selector. The graphite-based memristor are promising for high-density, low-power, selectorless RRAM array applications. The formation of GO with low dielectric constant of 4.3 is beneficial for high NL. The highly NL characteristics observed in graphite-based bilayer devices are desirable in suppressing sneak-path currents in crossbar arrays.