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(Invited) 3D Circuitry and Folding with 2D Crystals

Thursday, 17 May 2018: 08:20
Room 201 (Washington State Convention Center)
J. Park (University of Chicago)
Two thousand years ago, the mass-manufacturing of paper simplified all aspects of information technology: generation, processing, communication, delivery and storage. Similarly powerful changes have been seen in the last century through the development of integrated circuits based on silicon. Monolayers of 2D crystals provide an ideal material platform for realizing these integrated circuits thin and free-standing, which were the key advantages of paper over other medium two thousand years ago. Once realized, these atomically thin circuits will be foldable and actuatable, which will further increase the device density and functionality, allowing them to be used tether-free (or wirelessly) in environments not previously accessible to conventional circuits, such as water, air or in space. In this talk, we will discuss our recent progresses toward building atomically-thin integrated circuits using wafer-scale 2D crystals. In order for this, we developed a series of approaches that are scalable, precise, and modular. We developed wafer-scale synthesis of three atom thick semiconductors, reported a wafer-scale patterning method for one-atom-thick lateral heterojunctions, and showed how atomically thin films and devices can be vertically stacked to form more complicated 3D circuitry. Then we will discuss our most recent efforts to turn these 2D circuits into 3D structures.