1470
(Invited) Pixel-Parallel 3-D Integrated CMOS Image Sensors for Next-Generation Video Systems

Tuesday, 15 May 2018: 08:50
Room 309 (Washington State Convention Center)
M. Goto, Y. Honda, T. Watabe, K. Hagiwara, M. Nanba, Y. Iguchi (NHK Science and Technology Research Laboratories), T. Saraya (The University of Tokyo), M. Kobayashi (Institute of Industrial Science, The University of Tokyo), E. Higurashi, H. Toshiyoshi (The University of Tokyo), and T. Hiramoto (Institute of Industrial Science, The University of Tokyo)
Performances of image sensors including pixel counts, capturing speed, and dynamic range continue improving to meet the demands for high-reality video systems such as 8K/4K television and three-dimensional (3-D) imaging. Recent 3-D integration technology of silicon device has boosted sensor performances by using through-silicon vias (TSVs) and micro-bumps [1-2]. However, fully parallel signal processing has not been possible yet because the size of TSVs or micro-bumps is larger than the imaging pixel.

We have proposed a new 3-D integration technology without using TSV or micro-bumps but by using direct bonding of silicon-on-insulator (SOI) wafers, in which gold electrodes are embedded in the SiO2 intermediate layer. The gold electrodes formed by the damascene process with chemical mechanical polishing (CMP) can be reduced to 1 μm or less in diameter. This 3-D integration technology enables us to develop pixel-parallel 3-D integrated CMOS image sensors [3-5] as illustrated in Fig. 1. Two SOI wafers are stacked and directly connected by the embedded gold electrodes within every pixel. We have also developed novel in-pixel A/D converters (ADCs) with pulse frequency output, where signal charges generated in photodiodes (PDs) are converted into pulse signals at a frequency corresponding to the input illuminance. The ADC has an advantage of wide dynamic range of illuminance because the signal charge accumulated in the PD is never saturated in principle.

Prototype sensors of 128 × 96 resolution were developed with 80-μm square pixel each and 10-μm diameter gold electrodes. The upper layer was assigned for the PDs and ADCs, and the lower was for the 16-bit pulse counters. The two wafers were bonded by an image recognition of infra-red camera, where we achieved alignment accuracy as high as 1 μm or better. We evaluated the sensor and confirmed an excellent linear output with a wide dynamic range of 96 dB, which corresponds to the 16-bit output of the pulse counter. Fig. 2 shows an example image captured by the developed sensor. We successfully demonstrated the operation of the pixel-parallel sensor without any pixel defects.

In summary, a pixel-parallel 3-D integrated CMOS image sensor with pulse-frequency-output A/D converters was developed by using direct bonding of SOI wafers and embedded gold electrodes. The developed process is promising for image sensors with ultimate performances and various More-than-Moore type devices.

References

[1] T. Haruta et al., ISSCC, p. 76, 2017.
[2] T. Kondo et al., Symp. VLSI Tech. Dig., p. 90, 2015.
[3] M. Goto et al., IEEE Trans. Electron Devices, 62 (11), pp. 3530, 2015.
[4] M. Goto et al., ECS trans., 61 (6), p. 87, 2014.
[5] M. Goto et al., IEDM, 4.2, 2014.