Amorphous Indium Gallium Zinc Oxide (a-IGZO) based thin film transistors (TFTs) are the most suitable switching devices for flexible electronics due to their compatibility with room temperature processing with high yield, high field-effect mobility (μ_fe), low threshold voltage (V_TH) and subthreshold swing (SS).¹ Many prospective applications have been reported using metal-oxide thin-film transistors such as RFID² and high-resolution displays³.

The biggest challenges of a-IGZO TFTs are the process repeatability due to the ambient sensitivity of IGZO, for example to contamination by hydrogen, oxygen, or nitrogen, which affect device performance and reliability. It has been reported that the addition of hydrogen atoms, which act as donors, shifts the transfer characteristics negatively due to enhancing the n-type free carriers.⁴ On the contrary the addition of oxygen, which acts as an acceptor, shifts the transfer positively by suppressing the free carriers. In PVD deposited a-IGZO TFTs, oxygen partial pressure is a key parameter to control the turn-on voltage and field-effect mobility. Annealing either post-fabrication or mid-process can also provide controllability. Interface formation around very thin IGZO films plays a big role on performance and reliability. It is now important to investigate the quantitative measurement of charge distribution/density-of-states (DoS) in IGZO material/interfaces, especially within the depletion regime in thin-film transistors to understand any correlation between device reliability and charges in the depletion regime. Commonly positive bias stress (PBS) shifts the transfer characteristic positively. The origin is explained as the negative charge (electron) traps or migration around the interfaces. The migration process has been attributed to the transformation of the ionized positive charge state (V_O²⁺ + 2e^-) to neutral oxygen vacancy state (V_O) by capturing two free electrons. ^5,6 Negative bias illumination stress (NBIS) conversely shifts the transfer characteristics negatively due to the creation/formation of positive charges (V_O to V_O²⁺ + 2e^-) in the channel region.¹

In our investigation, the depletion regime interface charge, bulk charge, and DoS distribution in pristine a-IGZO devices has been quantified using electrical measurements. To do this, we added an extra contact in the IGZO TFTs at the same time as patterning the source/drain metal in a coplanar top gate device architecture. During gate voltage dependent drain current measurement, we measured the potential changes in the extra contact point (between source & drain) using a high input impedance measurement channel which directly provides information on the depletion regime charges around the interface, since the potential proportionally represents the charge. With a gate voltage of -6V and source/drain voltage of 0V the measured potential at the extra probe is -0.47V (representing a charge density in depletion regime of ~ 8.5 x 10^-7 C/cm²), which gradually increased to ~0V as the gate voltage increased to -0.2V. The decrement/increment of depletion regime charges under PBS/NBIS, will provide the correct interpretation about the origin of device instabilities. For -0.2V to +6V gate voltage the extra probe channel potential depends on drain voltage and the position between the source and drain.

This appears to be a very simple measurement to understand the depletion regime charges in wide bandgap amorphous metal oxide thin film transistor, which is not possible using conventional capacitance-voltage and Kelvin probe potential measurement.⁷

References:

1. M. D. H. Chowdhury, P. Migliorato and J. Jang: Appl. Phys. Lett., Vol. 102, p.143506 (2013).
2. B-D. Yang, J-M. Oh, H-J, Kang, S-H. Park, C-S. Hwang, M. K. Ryu, and J-E. Pi, ETRI Journal, Vol. 35, p. 610 (2013).
3. D. Kim, Y. Kim, S. Lee, M. S. Kang, D. H. Kim, and H. Lee, J. of Electron Device Society, Vol.5, p.372 (2017).
4. M. D. H. Chowdhury, M. Mativenga, J. G. Um, R. K. Mruthyunjaya, G. N. Heiler, T. J. Tredwell, and J. Jang, IEEE Transactions on Electron Devices, Vol. 62, p. 869 (2015).
5. K. M. Niang, P. M. C. Barquinha, R. F. P. Martins, B. Cobb, M. J. Powell, and A. J. Flewitt, Appl. Phys. Lett. Vol.108, P. 093505 (2016).
6. M. D. H. Chowdhury, P. Migliorato and J. Jang: Appl. Phys. Lett., Vol 98, p.153511 (2011).
7. Z. Han, G. Xu, W. Wang, C. Lu, N. Lu, Z. Ji, L. Li, and M. Liu, Appl. Phys. Lett. Vol.109, P.023509 (2016).

Figure Caption:

Gate voltage dependent channel potential at extra probe terminal, current flow between gate to source and depletion regime charges (Gate Insulator Capacitance*(channel potential-gate voltage), while drain and source voltage was kept to 0V.